A 4 GHz quadrature output fractional-N frequency synthesizer for an IR-UWB transceiver

This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB transceiver.Designed in a 0.18μm mixed-signal & RF 1P6M CMOS process, the operating range of the synthesizer is 3.74 to 4.44 GHz. By using an 18-bit third-order ∑-△ modulator, the synthesizer achieves a frequency resolution of 15 Hz when the reference frequency is 20 MHz. The measured amplitude mismatch and phase error between I and Q signals are less than 0.1 dB and 0.8° respectively. The measured phase noise is -116 dBc/Hz at 3 MHz offset for a 4 GHz output.Measured spurious tones are lower than -60 dBc. The settling time is within 80 μs. The core circuit conupSigmaes only 38.2 mW from a 1.8 V power supply.     

使用三位三阶Δ∑调制器的集成1GHz小数频率合成器

本文实现了一个采用三位三阶Δ∑调制器的高频谱纯度集成小数频率合成器.该频率合成器采用了模拟调谐和数字调谐组合技术来提高相位噪声性能,优化的电源组合可以避免各个模块之间的相互干扰,并且提高鉴频鉴相器的线性度和提高振荡器的调谐范围.通过采用尾电流源滤波技术和减小振荡器的调谐系数,在片压控振荡器具有很低的相位噪声,而通过采用开关电容阵列,该压控振荡器达到了大约100MHz的调谐范围,该开关电容阵列由在片数字调谐系统进行控制.该频率合成器已经采用0.18μm CMOS工艺实现,仿真结果表明,该频率频率合成器的环路带宽约为14kHz,最大带内相位噪声约为-106dBc/Hz;在偏离载波频率100kHz处的相位噪声小于-120dBc/Hz,具有很高的频谱纯度.该频率合成器还具有很快的反应速度,其锁定时间约为160μs.     

一种高分辨率∑△小数分频频率合成器

提出了一种采用新型分频器的小数分频频率合成器。该频率合成器与传统的小数分频频率合成器相比具有稳定时间快、工作频率高和频率分辨率高的优点。设计基于TSMC0.25μm2.5V1P5MCMOS工艺,采用sig-ma-delta调制的方法实现。经测量得到该频率合器工作频率在2.400～2.850GHz之间,相位噪声低于-95dBc/Hz@100kHz,最小频率步进小于30Hz,开关时间小于50μs,满足多数无线通信系统的要求。     

一种用于短距离器件的带自校准的∑-Δ分数分频频率综合器

介绍了一种应用于433/868MHz频段短距离器件的分数分频频率综合器.采用带自适应频率校准的宽带压控振荡器来覆盖要求的频段,并采用3位量化、3阶的Σ△调制器来实现分数分频和改善锁相环的带外噪声.测试结果表明,自适应频率校准能够正常工作,压控振荡器的频率调节范围为1.31～1.18GHz,在3MHz频偏处的带外噪声为-139dBc/Hz,分数毛刺低于-60dBc.芯片采用0.35μm CMOS工艺,芯片面积仅为1.8mm2,功耗仅为57mW.     

一种用于双波段GPS接收机的低功耗宽带CMOS频率合成器

提出了一种用于双波段GPS接收机的宽带CMOS频率合成器.该GPS接收机芯片已经在标准O.18μm射频CMOS工艺线上流片成功,并通过整体功能测试.其中压控振荡器可调振荡频率的覆盖范围设计为2～3.6GHz,覆盖了L1,L2波段的两倍频的频率点.并留有足够的裕量以确保在工艺角和温度变化较大时能覆盖所需频率.芯片测试结果显示,该频率综合器在L1波段正常工作时的功耗仅为5.6mW,此时的带内相位噪声小于-82dBc/Hz,带外相位噪声在距离3.142G载波1M频偏处约为-112dBc/Hz,这些指标很好地满足了GPS接收芯片的性能要求.     

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate in a wide-band frequency range, a switched-capacitors bank LC tank voltage-controlled oscillator (VCO) and an adaptive frequency calibration (AFC) technique are used. The measured VCO tuning range is as wide as 600 MHz (40%) from 1.15 to 1.75 GHz with a tuning sensitivity from 5.2 to 17.5 MHz/V. A 3-bit fourth-order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz as well as agile switching time. The experimental results show -80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129 dBc/Hz out-of-band phase noise at 400-kHz offset frequency. The fractional spurious is less than -70 dBc/Hz at 300-kHz offset frequency and the reference spur is -75 dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.     

An agile ISM band frequency synthesizer with built-in GMSK datamodulation

In this paper, a high-resolution fractional-N RF frequency synthesizer is presented which is controlled by a fourth-order digital sigma-delta modulator. The high resolution allows the synthesizer to be digitally modulated directly at RF. A simplified digital filter which makes use of sigma-delta quantized tap coefficients is included which provides built-in GMSK pulse shaping for data transmission. Quantization of the tap coefficients to single-bit values not only simplifies the filter architecture, but the fourth-order digital sigma-delta modulator as well. The synthesizer makes extensive use of custom VLSI, with only a simple off-chip loop filter and VCO required. The synthesizer operates from a single 3-V supply, and has low power consumption. Phase noise levels are less than -90 dBc/Hz at frequency offsets within the loop bandwidth. Spurious components are less than -90 dBc/Hz over a 19.6-MHz tuning range     

An integrated 0.38–6 GHz, 9–12 GHz fully differential fractional-N frequency synthesizer for multi-standard reconfigurable MIMO communication application

A wide-band fully differential fractional-N frequency synthesizer for multi-standard application is presented. The single fully differential LC–VCO with 28.5 % tuning rang and a set of dividers, quadrature self-mixer are designed to accomplish the multi-frequency bands with the frequency band from 0.38 to 6 GHz and from 9.0 to 12 GHz. It covers several wireless standards. A novel high isolation multiplexer is presented to achieve the frequency band selection. This chip was implemented with 65 nm CMOS technology and the maximum consumption is 20.05 mA from 1.2 V power supply. It occupies an active area of 1.5 mm². The measured typical phase noise of the frequency synthesizer is ?114.6 dBc/Hz from 1 MHz offset for 4.85 GHz output.     

An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with<10-Hz RF carrier resolution

A 2.5-GHz/900-MHz dual fractional-N/integer-N frequency synthesizer is implemented in 0.35-μm 25-GHz BiCMOS. A ΔΣ fractional-N synthesizer is employed for RF channels to have agile switching, low in-band noise, and fine frequency resolution. Implementing two synthesizers with an on-chip ΔΣ modulator in a small package is challenging since the modulator induces substantial digital noise. In this work, several design aspects regarding noise coupling are considered. The fractional-N synthesizer offers less than 10-Hz frequency resolution having the in-band noise contribution of -88 dBc/Hz for 2.47-GHz output frequency and -98 dBc/Hz for 1.15-GHz output frequency, both measured at 20-kHz offset frequency. The prototype dual synthesizer consumes 18 mW with 2.6-V supply     

A 1.5-V 900-MHz monolithic CMOS fast-switching frequencysynthesizer for wireless applications

A new architecture for phase-locked loop frequency synthesizers which employs a switchable-capacitor array to tune the output frequency and a dual-path loop filter operating in the capacitance domain is proposed. It provides many advantages, including simplified analog circuitry, low supply voltage, low power consumption, small chip area, fast frequency switching, and high immunity of substrate noise. Implemented in a standard 0.5-μm CMOS process, a fully integrated fractional-N synthesizer prototype with a third-order sigma-delta modulator is designed for 1.5 V and consumes 30 mW. The total chip area is, 0.9 × 1.1 mm². The settling time is less than 100 μs and the phase noise is -118 dBc/Hz at 600-kHz offset     

一个自调谐,自适应的1.9GHz分数/整数频率综合器

本文提出了一个具有自调谐,自适应功能的1.9GHz的分数/整数锁相环频率综合器.该频率综合器采用模拟调谐和数字调谐相结合的技术来提高相位噪声性能.自适应环路被用来实现带宽自动调整,可以缩短环路的建立时间.通过打开或者关断 ΣΔ 调制器的输出来实现分数和整数分频两种工作模式,仅用一个可编程计数器实现吞脉冲分频器的功能.采用偏置滤波技术以及差分电感,在片压控振荡器具有很低的相位噪声;通过采用开关电容阵列,该压控振荡器可以工作在1.7GHz~2.1GHz的调谐范围.该频率综合器采用0.18 μ m,1.8V SMIC CMOS工艺实现.SpectreVerilog仿真表明:该频率综合器的环路带宽约为100kHz,在600kHz处的相位噪声优于-123dBc/Hz,具有小于15 μ s的锁定时间.     

A 1.78–3.05?GHz fractional-N frequency synthesizer with power reduced multi-modulus divider

Nowadays, multi-band frequency synthesizers are very popular for their compatibility, which lowers the chip cost. In this article, a low power 2.4?GHz broadband fractional-N frequency synthesizer based on ???C?? modulation is presented. A novel power reduced multi-modulus divider based on 2/3 divider cells is presented. The ??mod?? signals are employed to dynamically control the current of the end-of-cycle logic blocks in 2/3 divider cells. When the end-of-cycle logic blocks have no contribution to the divider operation, they are turned off to save power. The saved power is more than 30% in the desired division ratio range. A dual-band voltage controlled oscillator with switched capacitor arrays is designed to cover a wide tuning range. Other circuits such as phase frequency detector, charge pump and loop filter are also integrated on the chip. The whole frequency synthesizer has been fabricated in Chartered 0.18???m RF CMOS process. Tested results show it covers the tuning range from 1.78 to 3.05?GHz, with phase noise smaller than ?85 dBc/Hz at 100?kHz offset, and smaller than ?115 dBc/Hz at 3?MHz offset. Its power consumption is only 9.2?mW under 1.8?V supply voltage, and the chip occupies an area of 1.2?mm?×?1.3?mm.     

A CMOS monolithic ΔΣ-controlled fractional-N frequencysynthesizer for DCS-1800

A monolithic 1.8-GHz ΔΣ-controlled fractional-N phase-locked loop (PLL) frequency synthesizer is implemented in a standard 0.25-μm CMOS technology. The monolithic fourth-order type-II PLL integrates the digital synthesizer part together with a fully integrated LC VCO, a high-speed prescaler, and a 35-kHz dual-path loop filter on a die of only 2×2 mm². To investigate the influence of the ΔΣ modulator on the synthesizer's spectral purity, a fast nonlinear analysis method is developed and experimentally verified. Nonlinear mixing in the phase-frequency detector (PFD) is identified as the main source of spectral pollution in ΔΣ fractional-N synthesizers. The design of the zero-dead zone PFD and the dual charge pump is optimized toward linearity and spurious suppression. The frequency synthesizer consumes 35 mA from a single 2-V power supply. The measured phase noise is as low as -120 dBc/Hz at 600 kHz and -139 dBc/Hz at 3 MHz. The measured fractional spur level is less than -100 dBc, even for fractional frequencies close to integer multiples of the reference frequency, thereby satisfying the DCS-1800 spectral purity constraints     

具有量化噪声抑制的小数分频器

介绍了一款用于分数分频频率综合器的具有量化噪声抑制功能的小数分频器。使用4/4.5双模预分频器,将分频步长降为0.5,使带外相位噪声性能提高6 dB。ΣΔ调制器和分频器的配合使用一种非常简单的编程方式。采用同步电路消除异步分频器的抖动。采用该分频器的频率综合器在SMIC 0.18μm RF工艺下实现,芯片面积为1.47 mm×1 mm。测试结果表明,该频率综合器可以输出1.2～2.1 GHz范围的信号。测试的带内相位噪声小于-97 dBc/Hz,在1 MHz频偏处的带外相位噪声小于-124 dBc/Hz。在1.8 V的电源电压下,消耗的电流为16 mA。     

UHF RFID阅读器中低噪声Σ小数频率综合器的设计

采用0.18μmRF CMOS工艺结合EPC C1G2协议和ETSI规范要求,实现了一种应用于CMOS超高频射频识别阅读器中的低噪声ΔΣ小数频率综合器。基于三位三阶误差反馈型ΔΣ解调器,采用系数重配技术,有效提高频率综合器中频段噪声性能;关键电路VCO的设计过程中采用低压差调压器技术为VCO提供稳定偏压,提高了VCO相位噪声性能。多电源供电模式下全芯片偏置电流为9.6mA,测得在中心频率频偏200kHz、1MHz处,相处噪声分别为-108dBc/Hz和-129.8dBc/Hz。     

基于0.35μm SiGe BiCMOS的高纯度频率综合器

介绍了一个基于0.35μm SiGe BiCMOS的整数N频率综合器.通过采用不同工艺来实现不同模块,实现了一个具有良好的杂散和相噪性能的高纯度频率综合器.除环路滤波器外所有的部件均采用差分电路结构.为了进一步减小相位噪声,压控振荡器中采用绑定线来形成谐振.该频率综合器可在2.39～2.72 GHz的频率范围内输出功率OdBm.在100kHz频偏处测得的相位噪声为-95dBc/Hz,在1MHz频偏处测得的相位噪声为-116dBc/Hz.参考频率处杂散小于-72dBc.在3V 的工作电压下,包括输出驱动级在内的整个芯片消耗60mA电流.     

A wideband frequency synthesizer for a receiver application at multiple frequencies

An integer-N frequency synthesizer for a receiver application at multiple frequencies was implemented in 0.18 μm IP6M CMOS technology. The synthesizer generates 2.57 GHz, 2.52 GHz, 2.4 GHz and 2.25 GHz local signals for the receiver. A wide-range voltage-controlled oscillator (VCO) based on a reconfigurable LC tank with a binary-weighted switched capacitor array and a switched inductor array is employed to cover the desired frequencies with a sufficient margin. The measured tuning range of the VCO is from 1.76 to 2.59 GHz. From the carriers of 2.57 GHz,2.52 GHz, 2.4 GHz and 2.25 GHz, the measured phase noises are -122.13 dBc/Hz, -122.19 dBc/Hz, -121.8 dBc/Hz and -121.05 dBc/Hz, at 1 MHz offset, respectively. Their in-band phase noises are -80.09 dBc/Hz, -80.29 dBe/Hz,-83.05 dBc/Hz and -86.38 dBc/Hz, respectively. The frequency synthesizer including buffers consumes a total power of 70 Mw from a 2 V power supply. The chip size is 1.5 × 1 mm~2.     

A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO

A 1.8 GHz fractional-N frequency synthesizer implemented in 0.6 /spl mu/m CMOS with an on-chip multiphase voltage-controlled oscillator (VCO) exhibits no spurs resulting from phase interpolation. The proposed architecture randomly selects output phases of a multiphase VCO for fractional frequency division to eliminate spurious tones. Measured phase noise at 1.715 GHz is lower than -80 dBc/Hz within a 20 kHz loop bandwidth and -118 dBc/Hz at 1 MHz offset with no fractional spurs above -70 dBc/Hz. The synthesizer has a frequency resolution step smaller than 10 Hz. The chip consumes 52 mW at 3.3 V and occupies 3.7 mm/spl times/2.9 mm.     

A wideband low power low phase noise dual-modulus prescaler

This paper describes a novel divide-by-32/33 dual-modulus prescaler(DMP).Here,a new combination of DFF has been introduced in the DMP.By means of the cooperation and coordination among three types,DFF, SCL,TPSC,and CMOS static flip-flop,the DMP demonstrates high speed,wideband,and low power consumption with low phase noise.The chip has been fabricated in a 0.18-μm CMOS process of SMIC.The measured results show that the DMP’s operating frequency is from 0.9 to 3.4 GHz with a maximum power consumption of 2.51 mW under a 1.8 V power supply and the phase noise is -134.78 dBc/Hz at 1 MHz offset from the 3.4 GHz carrier.The core area of the die without PAD is 57×30μm~2.Due to its excellent performance,the DMP could be applied to a PLL-based frequency synthesizer for many RF systems,especially for multi-standard radio applications.     

一种UHF频段小数分频频率综合器设计与实现

基于130 nm CMOS工艺设计了一款特高频(UHF)频段的锁相环型小数分频频率综合器.电感电容式压控振荡器(LC VCO)片外调谐电感总值为2 nH时,其输出频率范围为1.06～1.24 GHz,调节调谐电感拓宽了频率输出范围,并利用开关电容阵列减小了压控振荡器的增益.使用电荷泵补偿电流优化了频率综合器的线性度与带内相位噪声.此外对电荷泵进行适当改进,确保了环路的稳定.测试结果表明,通过调节电荷泵补偿电流,频率综合器的带内相位噪声可优化3 dB以上,中心频率为1.12 GHz时,在1 kHz频偏处的带内相位噪声和1 MHz频偏处的带外相位噪声分别为-92.3和-120.9 dBc/Hz.最小频率分辨率为3 Hz,功耗为19.2 mW.