Si/CdTe复合衬底HgCdTe液相外延材料的生长与性能分析

通过改进推舟液相外延技术,成功地在(211)晶向Si/CdTe复合衬底上进行了HgCdTe液相外延生长,获得了表面光亮的HgCdTe外延薄膜.测试结果表明,(211)Si/CdTe复合衬底液相外延HgCdTe材料组分及厚度的均匀性与常规(111)CdZnTe衬底HgCdTe外延材料相当;位错腐蚀坑平均密度为(5～8)×105 cm-2,比相同衬底上分子束外延材料的平均位错密度要低一个数量级;晶体的双晶半峰宽达到70″左右.研究结果表明,在发展需要低位错密度的大面积长波HgCdTe外延材料制备技术方面,Si/CdTe复合衬底HgCdTe液相外延技术可发挥重要的作用.     

Si基CdTe复合衬底分子束外延研究

文章引入晶格过渡的Si/ZnTe /CdTe作为复合外延基底材料,以阻挡Si/HgCdTe之间大晶格失配产生的高密度位错。通过对低温表面清洁化、面极性控制和孪晶抑制等的研究,解决了Si基CdTe分子束外延生长中诸多的技术难题。在国内首次采用分子束外延(MBE)的方法获得了大面积的Si基CdTe复合衬底材料,对应厚度为4～4. 4μm Si/CdTe (211)样品双晶半峰宽的统计平均结果为83弧秒,与相同厚度的GaAs/CdTe (211)双晶平均水平相当。     

CdTe/Si复合衬底Ex-situ退火研究

复合衬底CdTe/ZnTe/Si的晶体质量是导致随后外延的HgCdTe外延膜高位错密度的主要原因之一,因此如何提高复合衬底CdTe/Si晶体质量是确保硅基碲镉汞走上工程化的关键所在。降低复合衬底CdTe/Si位错密度方法一般有:生长超晶格缓冲层、衬底偏向、In-situ退火和Ex-situ退火等,本文主要研究Ex-situ退火对复合衬底CdTe/Si晶体质量的影响。研究表明复合衬底经过Ex-situ退火后位错密度最好值达4.2×105cm-2,双晶半峰宽最好值达60arcsec。     

红外探测器材料Ⅱ

一、HgCdTe的外延与分子束外延生长 1.用MOVPE生长在(211)B CdTe/Si衬底上的HgCdTe膜层的特性(S.H.Suh等,韩国科技研究所)     

偏转角(211)Si基CdTe复合衬底研究

晶面偏角是提高(211) Si基CdTe复合衬底质量的方法之一。通过对偏转角Si基CdTe复合衬底分子束外延工艺的研究,发现2°和3°偏转角(211)Si基CdTe复合衬底在晶体质量方面优于标准(211)Si基CdTe复合衬底,是未来提高Si基CdTe复合衬底质量的新方向。     

采用(211)碲锌镉衬底制备碲镉汞液相外延薄膜

文中对(211)晶向的CdZnTe衬底进行液相外延生长HgCdTe。获得的碲镉汞液相外延材料的组分为0. 30 ～0. 33,薄膜厚度为10 ～15μm,表面缺陷密度为500cm- 2 ,材料的FWHM达到24弧秒,位错腐蚀坑密度约为2 ×105 cm- 2 ,该材料的表面形貌与采用(111)晶向衬底的HgCdTe外延材料有较大区别。     

Si基CdTe/HgCdTe分子束外延材料的位错抑制

基于GaAs/Si材料中位错的运动反应理论,修正获得CdTe/Si和HgCdTe/Si外延材料中的位错运动反应模型.采用快速退火方法对Si基HgCdTe外延材料进行位错抑制实验研究,实验结果与理论曲线基本吻合,从理论角度解释了不同高温热处理条件对材料体内位错的抑制作用.对于厚度为4～10μnn的CdTe/Si进行500...     

Si基大面积碲镉汞分子束外延研究

文章报道了Si基碲镉汞分子束外延(MBE)的最新研究进展。尝试用晶向偏角降低高界面应变能的方法,摸索大失配体系中位错的抑制途径,寻找位错密度与双晶半峰宽的对应关系,基本建立了外延材料晶体质量无损检测评价标准,并对外延工艺进行指导。通过上述研究,15~20μm Si基CdTe复合材料双晶半峰宽最好结果为54arcsec,对应位错密度(EPD)小于2×106/cm2,与相同厚度的GaAs/CdTe(211)双晶水平相当,达到或优于国际最好结果。获得的3 in 10μm Si基HgCdTe材料双晶半峰宽最好结果为51arcsec,目前Si基HgCdTe材料已经初步应用于焦平面中波320×240器件制备。     

在兰宝石衬底上金属有机外延生长CdTe和HgCdTe薄膜

红外探测系统中的光敏元件需要HgCdTe外延膜。通常,HgCdTe生长于CdTe衬底上,这种衬底具有能与HgCdTe晶格紧密匹配且又能不受HgCdTe膜自动掺杂影响的诱人性能。但是,CdTe衬底昂贵、脆、不能得到大的面积且与平常得到的衬底如Si、GaAs、Al_2O_3(兰宝石)或InSb相比结晶质量较差。因此需要另选一种基片材料。兰宝石就是一种诱人的候选者,这是因为它的结晶质量高、成本低、有刚度且能得到大的面积。液相外延技术是外延生长HgCdTe用的最普通的技术。然而,由于生长的熔料不能湿润兰宝石衬底,从而防碍了在兰宝石衬底上液相外延生长。为在兰宝石衬底上生长薄膜,最近     

分子束外延CdTe（211）B／Si复合衬底材料

报道了用MBE的方法，在3英寸Si衬底上制备ZnTe／CdTe（211）B复合衬底材料的初步研究结果，该研究结果将能够直接应用于大面积Si基HgCdTe IRFPA材料的生长．经过Si（211）衬底低温表面处理、ZnTe低温成核、高温退火、高温ZnTe、CdTe层的生长研究，用MBE方法成功地获得了3英寸Si基ZnTe／CdTe（211）B复合衬底材料．CdTe厚度大于10μm，XRD FWHM平均值为120arc sec，最好达到100arc sec，无（133）孪晶和其他多晶晶向．     

Lattice mismatch induced morphological features and strain in HgCdTe epilayers on CdZnTe substrates

HgCdTe epilayers on CdZnTe substrates can exhibit a cross-hatch pattern of periodically varying strain and surface undulations as revealed by x-ray topography, and in some cases by Nomarski optical microscopy. On { 111 } oriented material, the pattern appears as three sets of parallel lines in the 〈 110 〉 slip directions (60° apart). To investigate this phenomenon and its impact on photovoltaic device performance, we have characterized several liquid phase epitaxy (LPE)-grown HgCdTe epilayer samples by means of Lang x-ray reflection topography, synchrotron white beam x-ray topography (SWBXT), etch pit density, and other techniques. The cross hatching generally shows a correlation with the ZnTe mole fraction of the substrate. In particular, the pattern is likely to appear when the natural lattice parameter of the layer at room temperature is slightly larger or smaller than that of the substrate in the same region. We also find the corresponding pattern in { 211 } oriented layers grown by MBE. Although substantial compositional interdiffusion occurs at the layer/substrate interface during LPE growth at around 500°C, this is not a necessary condition for the cross-hatch pattern, as demonstrated by the occurrence of the pattern in MBE material grown at less than 200°C. In terms of device performance, the pattern is manifested as lines of diodes in an array having greater leakage than their neighbors. In addition to these results, we have investigated other anomalies, by means of SWBXT applied to large-area diodes that have been electrically tested. A novel technique called absorption edge contour mapping, using synchrotron white beam x-rays with a molybdenum filter, was applied to reveal the longer range lattice strain.     

Substrate quality impact on the carrier concentration of undoped annealed HgCdTe LPE layers

The impact of Te precipitates and impurities, in CdZnTe or CdTe substrates, on grown liquid phase epitaxy (LPE) HgCdTe layer hole concentrations was studied. The carrier concentrations in capped annealed LPE HgCdTe layers grown on CdZnTe substrates with large densities of Te precipitates are frequently significantly higher than those expected for HgCdTe annealed under Hg-deficient conditions. The carrier concentration in the LPE layer, due to the diffusion of copper ions from contaminated CdTe substrates into the layer, is strongly affected by the polarity of the (111)-oriented substrates. Layers grown on the (111)A face showed very high concentrations of Cu, whereas in those grown on the (111)B face normal carrier concentrations were achieved. These phenomena are discussed on the basis of defects formed either in the epilayer or in the layer-substrate interface.     

昆明物理研究所大面积水平推舟液相外延碲镉汞薄膜技术进展

报道了近年来昆明物理研究所在富碲水平推舟液相外延碲镉汞外延薄膜制备技术方面的进展。2019年以来,突破了?120 mm碲锌镉晶体定向生长技术,使碲锌镉衬底沉积相和夹杂相密度≤5×103 cm－2,位错腐蚀坑密度（EPD）≤4.0×104 cm－2,?120 mm（111）晶圆衬底的Zn组份分布极差≤0.36%。基于碲锌镉衬底技术的进步,液相外延碲镉汞薄膜的最大生长尺寸达到了70 mm×75 mm,薄膜位错腐蚀坑密度均值为5×104 cm－2,X射线双晶回摆曲线半峰宽（DCRC-FWHM）≤35 arcsec,部分可控制到25 arcsec以下;50 mm×60 mm尺寸长波碲镉汞薄膜的厚度极差≤±1.25 μm,室温截止波长极差≤±0.1 μm,中波碲镉汞薄膜相应指标分别为≤±1 μm、≤±0.05 μm。材料技术的进展促进了制冷型碲镉汞探测器产能提升和成本的降低,也支撑了高性能长波/甚长波探测器、高工作温度（HOT）探测器以及2048×2048、4096×4096等甚高分辨率高性能探测器的研制。     

碲锌镉缓冲层液相外延技术的研究

文章报道了采用液相外延方法，在碲锌镉衬底上进行碲锌镉薄膜缓冲层生长的情况，并且采用X光双晶衍射仪、X光形貌仪、红外傅里叶光谱仪、二次离子质谱仪等手段对碲锌镉薄膜进行了表征，碲锌镉薄膜具有较好地组分及均匀性，晶体结构质量也较好。采用碲锌镉缓冲结构生长了碲镉汞液相外延片，其碲锌镉与碲镉汞薄膜界面附近的杂质得到了有效的控制。     

碲锌镉缓冲层液相外延技术的研究

文章报道了采用液相外延方法，在碲锌镉衬底上进行碲锌镉薄膜缓冲层生长的情况，并且采用X光双晶衍射仪、X光形貌仪、红外傅里叶光谱仪、二次离子质谱仪等手段对碲锌镉薄膜进行了表征，碲锌镉薄膜具有较好地组分及均匀性，晶体结构质量也较好。采用碲锌镉缓冲结构生长了碲镉汞液相外延片，其碲锌镉与碲镉汞薄膜界面附近的杂质得到了有效的控制。     

Direct growth of CdZnTe/Si substrates for large-area HgCdTe infrared focal plane arrays

Direct epitaxial growth of high-quality 100lCdZnTe on 3 inch diameter vicinal {100}Si substrates has been achieved using molecular beam epitaxy (MBE); a ZnTe initial layer was used to maintain the {100} Si substrate orientation. The properties of these substrates and associated HgCdTe layers grown by liquid phase epitaxy (LPE) and subsequently processed long wavelength infrared (LWIR) detectors were compared directly with our related efforts using CdZnTe/ GaAs/Si substrates grown by metalorganic chemical vapor deposition (MOCVD). The MBE-grown CdZnTe layers are highly specular and have both excellent thickness and compositional uniformity. The x-ray full-width at half-maximum (FWHM) of the MBE-grown CdZnTe/Si increases with composition, which is a characteristic of CdZnTe grown by vapor phase epitaxy, and is essentially equivalent to our results obtained on CdZnTe/GaAs/Si. As we have previously observed, the x-ray FWHM of LPE-grown HgCdTe decreases, particularly for CdZnTe compositions near the lattice matching condition to HgCdTe; so far the best value we have achieved is 54 arc-s. Using these MBE-grown substrates, we have fabricated the first high-performance LWIR HgCdTe detectors and 256 x 256 arrays using substrates consisting of CdZnTe grown directly on Si without the use of an intermediate GaAs buffer layer. We find first that there is no significant difference between arrays fabricated on either CdZnTe/Si or CdZnTe/GaAs/Si and second that the results on these Si-based substrates are comparable with results on bulk CdZnTe substrates at 78K. Further improvements in detector performance on Si-based substrates require a decrease in the dislocation density.     

Strain relief in epitaxial HgCdTe by growth on a reticulated substrate

In nearly all cases when an epitaxial layer of HgCdTe is grown on a CdZnTe substrate, there will be a finite lattice mismatch due to the lack of precise control over the ZnTe mole fraction. This leads to strains in the layer, which can be manifested in one or more ways: (1) as misfit dislocations near the interface, (2) as threading dislocations, (3) as surface topographical textures, and (4) as cross-hatch lines seen by x-ray topography. We have found that much of the strain can be relieved by growing on a reticulated substrate. Specifically, when the substrate has been etched to form mesas prior to growth of the layer, the resulting layer on the tops of the mesas shows evidence of significantly reduced strain. CdZnTe substrates oriented (111)A were prepared with two sets of mesas on 125 μm centers and 60 μm centers, and with other planar areas remaining for comparison. From a Hg melt, a layer of LWIR HgCdTe was grown about 16 μm thick on each substrate. Nomarski microscopy showed that the layers on the mesa tops were extremely flat, showing no sign of curvature or surface texture. X-ray topography showed no cross hatch on the mesa tops, while the usual cross hatch appeared in the planar regions. The LPE layer extended laterally beyond the edges of the original mesa because of faster growth in non-(111) directions. Samples were cleaved and examined in cross section. The linear density of etch pits seen in the cross section near the substrate, which represent misfit dislocations, was three times lower in the layer on the mesas than in the layer in the unpatterned region, although both regions have the same layer/substrate lattice mismatch. When an epilayer is grown on an unpatterned wafer (the conventional approach), the growth in any small region is confined laterally by the growing layer in the neighboring regions. However, when growth occurs on a reticulated surface, the lateral confinement is removed, providing strain relief and fewer defects.     

Te-rich liquid phase epitaxial growth of HgCdTe on Si-based substrates

The growth of high quality (111)B oriented HgCdTe layers on CdZnTe/GaAs/Si and CdTe/Si substrates by Te-rich slider liquid phase epitaxy (LPE) is reported. Although the (111) orientation is susceptible to twinning, a reproducible process yielding twin-free layers with excellent surface morphology has been developed. The electrical properties and dislocation density in films grown on these substrates are comparable to those measured in HgCdTe layers grown on bulk CdTe substrates using the same LPE process. This is surprising in view of the large lattice mismatch that exists in these systems. We will report details of both the substrate and HgCdTe growth processes that are important to obtaining these results.     

异质衬底外延碲镉汞薄膜位错抑制技术进展

分子束外延碲镉汞技术是制备第三代红外焦平面探测器的重要手段,基于异质衬底的碲镉汞材料具有尺寸大、成本低、与常规半导体设备兼容等优点,是目前低成本高性能红外探测器发展中的研究重点。对异质衬底上碲镉汞薄膜位错密度随厚度的变化规律进行了建模计算,结果显示ρ～1/h 模型与实验结果吻合度好,异质衬底上原生碲镉汞薄膜受位错反应半径制约,其位错密度无法降低至 5×10⁶cm^-2以下,难以满足长波、甚长波器件的应用需求。为了有效降低异质外延的碲镉汞材料位错密度,近年来出现了循环退火、位错阻挡和台面位错吸除等位错抑制技术,本文介绍了各技术的原理及进展,分析了后续发展趋势及重点。循环退火和位错阻挡技术突破难度大,发展潜力小,难以将碲镉汞位错密度控制在 5×10⁵cm^-2以内。台面位错吸除技术目前已经显示出了巨大的发展潜力和价值,后续与芯片工艺融合后,有望大幅促进低成本长波、中长波、甚长波器件的发展。