基于红外的微机器人集群自主通信转接控制方法

对多障碍物环境下微机器人集群自主通信转接的控制问题进行了研究.结合微机器人尺寸小的特点,采用低功耗的红外通信方式,利用载波侦听多路访问技术实现了多移动微机器人间的红外通信.在红外通信的基础上,建立了基于弹簧阻尼系统的自主通信转接控制模型,设计了相应的控制器以实现微机器人的运动控制,进而实现微机器人集群的自主通信转接.仿真结果验证了该控制方法的有效性.     

多晶体材料微构件尺度效应的实验和模型研究

归纳了微电子机械系统中多晶体材料微构件在微塑性加工和应用中其力学性能所表现出来的尺度效应及其多种尺寸关联的主要特征,介绍了微构件外形几何尺寸和材料内部微结构尺寸对其弹、塑性力学性能尺度效应耦合影响的实验和模型研究的主要进展。重点总结并分析了多晶体材料微构件越小越强和越小越弱两种类型尺度效应的研究方法以及测试、影响因素及微观机理初步分析的结果。结论是:微构件内、外尺寸的耦合关联影响控制了尺度效应和与其相对应的材料内在特征长度,今后如能进一步探明微构件外形结构尺寸、晶粒尺寸和材料内在特征长度与其性能异变之间的制约关系,基于晶体学和高阶理论建立较全面、系统的力学分析模型,将有可能揭示微构件多晶材料内在特征长度的微结构控制的机理,进而实现通过调控材料的微结构控制微构件的宏观力学性能。     

微型装配用的硅夹钳

高度柔性和可靠的夹钳与搬运机器人,广泛地应用在电子工业和机器制造的许多领域。然而,现有夹持工具的几何尺寸、造型及其控制,阻碍了夹持系统在微系统、微操作、微装配以及微并接技术中的应用。简单的解决办法也许是线性缩小传统的夹钳,但这是不可能实现的,因为,这方面需要的夹持系统本身,已属于微技术系统。所以需要在微技术基础之上寻求新的解决方案。     

利用低功耗比较器自动检测音频附件

利用MAX9060系列超小尺寸、微功耗比较器,通过不同的配置方式对便携式电子设备外部附件进行检测,不仅把功耗控制在可以忽略的等级,还为产品提供了一种小巧、简单、具有极高性价比检测方案.这一应用方案有助于降低系统的整体功耗.     

PCR-CE微流体芯片控制系统开发

本文设计具有DNA聚合酶链式反应(PCR)和毛细管电泳(CE)分离检测功能的微流体芯片控制系统.本系统采用32位嵌入式微控制器ARM实现PCR扩增所需的闭环温度控制功能,毛细管电泳分离所需的高压电场自动调度功能和毛细管电泳电化学检测功能.采用模糊免疫PID控制算法实现对温度的精确控制,其控制性能远优于常规PID控制器,实现了PCR-CE微流体芯片系统的低成本和小型化.     

具有微生物颗粒预富集功能的微过滤系统设计北大核心

为了提高微流式细胞仪对低浓度细胞样本液的检测效率和准确率,提出一种以电磁驱动的微过滤系统设计方案。该微过滤系统包括具有过滤结构的微流控芯片（微过滤芯片）和电磁驱动机构,借助电磁控制来实现微过滤芯片对微生物颗粒的富集功能。使用微电子机械系统（MEMS）工艺设计与制作了聚二甲基硅氧烷（PDMS）薄膜微过滤芯片,通过对微过滤芯片的受力分析,自制了一套电磁驱动装置。使用溶有直径为30μm荧光微球的去离子水溶液（荧光微球与去离子水的体积比1∶40）对微过滤系统样机进行功能测试,通过控制电流大小、通电时间对给定溶液中的荧光微球实现了预富集效果。测试结果表明该微过滤系统设计合理,具有制作简单,成本低、易于集成等优点,能够在医学检测中广泛应用。     

荧光磁粉探伤自动化检测系统

介绍了如何实现荧光磁粉探伤自动化检测系统。该系统在荧光磁粉探伤原理的基础上,以计算机作为中心控制系统,控制磁粉探伤机和步进电机,同时结合图像处理和机器视觉技术,对工件的金属壳体进行尺寸和缺陷检测。     

静电悬浮转子微陀螺五自由度位置检测研究

给出了一种基于微机电系统(MEMS)技术的静电悬浮转子微陀螺,为了实现对静电悬浮转子微陀螺转子的五自由度(5-DOF)悬浮控制,需要对转子进行五自由度位置检测,首先介绍了微位移检测原理,提出了一种基于频分复用技术和开关解调技术的微位移检测方法,设计了基于直接数字频率合成(DDS)技术的多频率信号发生器、前置放大器及锁相放大器组成的位置测试系统,位移检测电路的各项性能指标能满足静电悬浮转子微陀螺的五自由度控制需要.     

MEMS技术在流体控制中的应用

微机电系统(MEMS:Micro Electro-Mechanical System)技术或微传感器与微执行器(MicromachinedTranducers)技术,它是在微电子技术的基础上发展起来的,融合了硅微加工和精密机械加工等多种微加工技术,并利用IC技术把控制和信号处理电路与机械部件集成的微型系统。这种技术所涉及的器件的特征尺寸一般小于1mm而大于1μm,它为流体控制研究开辟了一个崭新的领域。简述了流体控制技术的基本原理以及应用MEMS技术实现流体控制的机理和途径,分别介绍了国外研究机构近年来在微传感、微执行技术的研究工作。     

基于模糊PID控制的PCB微钻检测系统

PCB微钻的检测需要对微钻的运动轨迹进行精密的控制,这里在直线电机驱动的模型下进行研究分析。通过建立直线伺服电动机推针机构的系统仿真模型,详细分析了模糊PID算法以及数学模型。分别用传统的PID控制与模糊PID控制,对推针装置的推针过程进行了仿真。结果表明,模糊PID控制器能较好地实现微钻的位置跟踪,使其按照预定的运动轨迹运动,提高了检测的精度。     

Appropriate buffer sizes for Internet nodal devices: A networks' topologies–based solution

Switched networks' (including the Internet) nodal devices require buffers to hold packets during periods of congestion and when traffic streams on more than one input port need to access the same output port. Appropriately sizing the buffers has been a contentious issue among researchers over the last couple of years. Three main buffer sizing formulas have been reported in literature, which are: bandwidth‐delay product or BDP, small buffer, and the tiny buffer formulas. But researchers are largely agreed that the BDP formula results in unrealistically large and wasteful buffers, while a number of researchers have held with good reasons, that the small and tiny buffer formulas are theoretical formulations that cannot be generally and practically applied to real networks. Some researchers have even asserted that deriving a single, universal formula for sizing buffers may not be possible. The main purpose of this paper is to explain an approach, which we term “network topology point –of –view,” that we developed to derive a novel, empirical, generic, practical, easy‐to‐apply, closed‐form formula that can be used to obtain the buffer capacity that is optimal—in terms of the minimum capacity possible for lossless operation, for any switched network node, including nodes (switches and routers) in the Internet. The results obtained from utilizing the formula to specify typical nodal buffers' capacities are largely in agreement with the values of the tiny buffer formula in literature; but this paper's formula additionally specifies what we term “very tiny buffers.” The simple approach adopted for presenting this paper makes it a handy tutorial material that explains this “network topology point‐of‐view” concept.     

施耐德ATV-IMC在浆纱机张力控制系统上的应用

本文介绍了浆纱机卷绕张力控制方法及施耐德ATV71变频器内置控制卡ATV-IMC张力控制功能块的应用,为浆纱机的张力控制提供了一种简单经济的方法。     

ABB变频器应用于G142型浆纱机两单元改造

本文介绍了G142型浆纱机改造成两单元的控制方案和调试步骤,以及ABB变频器控制系统、ABB变频器卷曲应用宏软件,HMI触控技术等在两单元浆纱机上的应用。     

Sizing of multi-stage Op Amps by combining design equations with the gm/ID method

Analog integrated circuit design has as integral parts both analytical reasoning and numerical validation in the process from topology construction to sizing. Given a circuit topology, different circuit sizing results can be obtained from different processes of sizing inference. Sizing methods by simulation-based numerical searching have been a continuously studied subject. However, almost all approaches in this category require an overwhelming number of circuit simulations to arrive at an optimized sizing result. On the other hand, many published manual sizing methods by using the conventional device equations also require repeated SPICE simulations to correct the equation-based sizing results. This paper proposes a systematic gm/ID-based initial sizing method specifically customized for designing multiple-stage operational amplifiers (Op Amps). A main feature of the proposal is to use circuit-level design equations as constraints on the gm/ID table lookup method to substantially reduce the uncertainty in the sizing calculations. As a result, a significant amount of SPICE based correction work can be reduced to complete an initial sizing. The proposed sizing procedure includes a few regular sizing rules customized to the configuration of multi-stage Op Amps. We validate the proposed sizing method by application to several multi-stage Op Amp examples with a capacitive load or Miller compensation. Simulations have justified that the produced initial sizing results can achieve most of the prespecified design targets.     

变频器在长丝浆丝机上的应用

本文简述了浆丝机的技术特征，重点介绍了浆丝机的控制系统，包括变频同步调速系统，PLC的主要功能和工艺参数的控制等。     

艾默生TD3300张力控制变频器应用于两单元浆纱机

本文介绍艾默生变频器控制系统,人机界面触控技术等在两单元浆纱机上的应用,以及有关的数学计算。     

Gate sizing using geometric programming

A two-step transistor sizing optimization method based on geometric programming for delay/area minimization is presented. In the first step, Elmore delay is minimized using only minimum and maximum transistor size constraints. In the second step, the minimized delay found in the previous step is used as a constraint for area minimization. In this way, our method can target simultaneously both delay and area reduction. Moreover, by relaxing the minimized delay, one may further reduce area with small delay penalty. Gate sizing may be accomplished through transistor sizing tying each transistor inside a cell to a same scale factor. This reduces the solution space, but also improves runtime as less variables are necessary. To analyze this tradeoff between execution time and solution quality a comparison between gate sizing and transistor sizing is presented. In order to qualify our approach, the ISCAS??85 benchmark circuits are mapped to a 45?nm technology using a typical standard cell library. Gate sizing and transistor sizing are performed considering delay minimization. Gate sizing is able to reduce delay in 21?%, on average, for the same area and power values of the sizing provided by standard-cells library. Then, the transistor sizing is executed and delay can be reduced in 40.4?% and power consumption in 2.9?%, on average, compared to gate sizing. However, the transistor sizing takes about 23 times longer to be computed, on average, using a number of variables twice higher than gate sizing. Gate sizing optimizing area is executed considering a delay constraint. Three delay constraints are considered, the minimum delay given by delay optimization and delay 1 and 5?% higher than minimum delay. An energy/delay gain (EDG) metric is used to quantify the most efficient tradeoff. Considering the minimum delay, area (power) is reduced in 28.2?%, on average. Relaxing delay by just 1?%, area (power) is reduced in 41.7?% and the EDG metric is 41.7. Area can be reduced in 51?%, on average, relaxing delay by 5?% and EDG metric is 10.2.     

A projection of future ATC data processing requirements

Forecast traffic growth for the 1980-1995 time period will exceed the capacity of the present airport and air traffic control automation system in high-density areas. If traffic growth is to be accommodated, higher levels of automation are required. The Department of Transportation Air Traffic Control Advisory Committee (September 1968-August 1969) established a computer sizing group to determine the feasibility of achieving the necessary level of automation within the projected technology. This paper presents a model of the future system, a summary of the functions automated, and estimates of the necessary computer instruction rate and storage requirements as developed by this computer sizing group.     

光微变及微光的光敏二极管探测电路的研究

光敏二极管的开路电压随光照强度的增加,成对数式增大,当光强在一定范围内变化时,开路电压随光强变化的斜率很大,利用此特性的光探测电路,对光强的微弱变化十分敏感,适用于侵入监测和需要准确监控光强变化的情况．分析比较了几种可用于光探测的运算放大器电路,提出了实现微光及光微变的光敏二极管探测的方案．     

VLSI互连线的全局优化算法

介绍了通过同时插入缓冲嚣和优化线宽达到互连线时延最小化的方法。为了同时插入缓冲器、优化缓冲嚣尺寸和优化线宽，可以扩展MASM(改进激活集合法)算法。计算结果表明，该算法非常有效。