Iterative threshold decoding without interleaving for convolutional self-doubly orthogonal codes

A novel iterative error control technique based on the threshold decoding algorithm and new convolutional self-doubly orthogonal codes is proposed. It differs from parallel concatenated turbo decoding as it uses a single convolutional encoder, a single decoder and hence no interleaver, neither at encoding nor at decoding. Decoding is performed iteratively using a single threshold decoder at each iteration, thereby providing good tradeoff between complexity, latency and error performance.     

New Syndrome Check Error Estimation and Its Concatenated Coding

A low-complexity and high performance SCEE (Syndrome Check Error Estimation) decoding method for convolutional codes and its concatenated SCEE/RS (Reed–Solomon) coding scheme are proposed. First, we describe the operation of the decoding steps in the proposed algorithm. Then deterministic values on the decoding operation are derived when some combination of predecoder-reencoder is used. Computer simulation results show that the computational complexity of the proposed SCEE decoder is significantly reduced compared to that of conventional Viterbi decoder without degradation of the P_e performance. Also, simulation results of BER performance of the concatenated SCEE/Hard Decision Viterbi (HD-Viterbi) and SCEE/RS (Reed–Solomon) codes are presented.     

Concatenated decoding with a reduced-search BCJR algorithm

We apply two reduced-computation variants of the BCJR algorithm to the decoding of serial and parallel concatenated convolutional codes. One computes its recursions at only M states per trellis stage; one computes only at states with values above a threshold. The threshold scheme is much more efficient, and it greatly reduces the computation of the BCJR algorithm. By computing only when the channel demands it, the threshold scheme reduces the turbo decoder computation to one-four nodes per trellis stage after the second iteration     

基于级联码的信道编译码设计与FPGA实现

介绍了RS(255,223)码级联卷积(4,3,3)码编译码器的实现,对于编码和译码端不同的结构特点.分别采用并行和串行结构实现.其中RS译码采用欧几里德算法,卷积译码采用维特比算法.同时给出了该编译码器的FPGA实现,按照自上而下的设计流程,在保证速度的同时最大限度地减少了资源占用.     

LDPC Decoding by Failed Check Nodes for Serial Concatenated Code

The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low‐density parity‐check (LDPC) codes. An enhanced sum–product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error‐correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of 10^?8. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.     

A multi-D trellis decoder for A 155 Mb/s concatenated codec

An implementation of a 16 state, rate 8/9 six-dimensional (6-D) 8PSK rotationally invariant trellis decoder for use in a concatenated codec is described. The concatenated codec allows transmission of STM-1 signals (at the 155.52 Mb/s information rate) over a 72 MHz satellite transponder. The inner trellis decoder is used with an outer (255,239) RS block decoder. The trellis decoder operates at 165.93 Mb/s and currently has an implementation loss of only 0.2 dB. The concatenated codec achieves a bit error ratio of 10^?10 at an Eb/N⁰ of 8.2 dB (assuming an ideal modem and AWGN channel). Details are given of many Viterbi decoding ‘tricks’ that were used in order to implement the main functions of the decoder on two 10,000 gate equivalent CMOS programmable gate arrays.     

Performance of parallel and serial concatenated codes on fading channels

The performance of parallel and serial concatenated codes on frequency-nonselective fading channels is considered. The analytical average upper bounds of the code performance over Rician channels with independent fading are derived. Furthermore, the log-likelihood ratios and extrinsic information for maximum a posteriori (MAP) probability and soft-output Viterbi algorithm (SOVA) decoding methods on fading channels are developed. The derived upper bounds are evaluated and compared to the simulated bit-error rates over independent fading channels. The performance of parallel and serial codes with MAP and SOVA iterative decoding methods, with and without channel state information, is evaluated by simulation over independent and correlated fading channels. It is shown that, on correlated fading channels, the serial concatenated codes perform better than parallel concatenated codes. Furthermore, it has been demonstrated that the SOVA decoder has almost the same performance as the MAP decoder if ideal channel state information is used on correlated Rayleigh fading channels.     

Asymptotic performance comparison of concatenated (turbo) codes over GF(4)

In this paper, we investigate and compare the asymptotic performance of concatenated convolutional coding schemes over GF(4) over additive white Gaussian noise (AWGN) channels. Both parallel concatenated codes (PCC) and serial concatenated codes (SCC) are considered. We construct such codes using optimal non‐binary convolutional codes where optimality is in the sense of achieving the largest minimum distance for a fixed number of encoder states. Code rates of the form k₀/(k₀ + 1) for k₀=1, 8, and 64 are considered, which suite a wide spectrum of communications applications. For all of these code rates, we find the minimum distance and the corresponding multiplicity for both concatenated code systems. This is accomplished by feeding the encoder with all possible weight‐two and weight‐three input information patterns and monitoring, at the output of the encoder, the weight of the corresponding codewords and their multiplicity. Our analytical results indicate that the SCC codes considerably outperform their counterpart PCC codes at a much lower complexity. Inspired by the superiority of SCC codes, we also discuss a mathematical approach for analysing such codes, leading to a more comprehensive analysis and allowing for further improvement in performance by giving insights on designing a proper interleaver that is capable of eliminating the dominant error patterns. Copyright © 2004 John Wiley & Sons, Ltd.     

Carrier phase recovery for turbo‐coded systems with pre‐coded GMSK modulation

A carrier phase recovery scheme suited for turbo‐coded systems with pre‐coded Gaussian minimum shift keying (GMSK) modulation is proposed and evaluated in terms of bit‐error‐rate (BER) performance. This scheme involves utilizing the extrinsic information obtained from the turbo‐decoder to aid an iterative carrier phase estimation process, based on a maximum‐likelihood (ML) strategy. The phase estimator works jointly with the turbo‐decoder, using the updated extrinsic information from the turbo‐decoder in every iterative decoding. A pre‐coder is used to remove the inherent differential encoding of the GMSK modulation. Two bandwidths of GMSK signals are considered: BT=0.5 and 0.25, which are recommended by the European Cooperation for Space Standardization (ECSS). It is shown that the performance of this technique is quite close to the perfect synchronized system within a wide range of phase errors. This technique is further developed to recover nearly any phase error in [?π,+π] by increasing the number of phase estimators and joint decoding units. This, however, will increase the complexity of the system. Copyright © 2008 John Wiley & Sons, Ltd.     

High Throughput Parallel Decoding Method for H.264/AVC CAVLC

A high throughput parallel decoding method is developed for context‐based adaptive variable length codes. In this paper, several new design ideas are devised and implemented for scalable parallel processing, a reduction in area, and a reduction in power requirements. First, simplified logical operations instead of memory lookups are used for parallel processing. Second, the codes are grouped based on their lengths for efficient logical operation. Third, up to M bits of the input stream can be analyzed simultaneously. For comparison, we designed a logical‐operation‐based parallel decoder for M=8 and a conventional parallel decoder. High‐speed parallel decoding becomes possible with our method. In addition, for similar decoding rates (1.57 codes/cycle for M=8), our new approach uses 46% less chip area than the conventional method.     

Implementation and performance of a turbo/MAP decoder

The implementation and performance of a turbo/MAP decoder are described. A serial block MAP decoder operating in the logarithm domain is used to obtain a very-high-performance turbo decoder. Programmable gate arrays and EPROMs allow the decoder to be programmed for almost any code from four to 512 states, rate 1/3 to rate 1/7 (higher rates are achieved with puncturing) and interleaver block sizes to 65,536 bits. Seven decoding stages were implemented in parallel. For rate 1/3 and 1/7 16-state codes with an interleaver size of 65,536 bits and operating at up to 356 kbit/s the codec achieved an E_b/N₀ of 0⋅32 and −0⋅30 dB respectively for a BER of 10⁻⁵. BERs down to 10⁻⁷ were also achieved for a small increase in E_b/N₀. An efficient implementation of a continuous MAP decoder is also presented, along with a synchronization technique for turbo decoders. © 1998 John Wiley & Sons, Ltd.     

Advanced decoding algorithms for Reed-Solomon/Convolutional concatenated codes

The evaluation of the union bound for theber of Reed-Solomon/Convolutional concatenated codes indicates that their performance might largely improve through the application of soft iterative decoders. This paper presents an iterative decoding algorithm for concatenated codes consisting of an outer Reed-Solomon code, a symbol interleaver and an inner convolutional code. The performance improvement for iterative and non-iterative decoders is evaluated. Existing solutions for the different decoding stages and their interfaces are discussed and their performance is compared. A new procedure is proposed to define the feedback signal from the output of the Reed-Solomon decoder to the input of the convolutional decoder, which captures the reliability information that can be inferred from errors-and-era-suresrs decoders and includes the “state pinning” approach as a particular case. The decoding schemes are applied to the specificdvb-s concatenated code.     

A Subthreshold PMOS Analog Cortex Decoder for the (8, 4, 4) Hamming Code

This paper presents a method for decoding high minimal distance (d_min) short codes, termed Cortex codes. These codes are systematic block codes of rate 1/2 and can have higher d_min than turbo codes. Despite this characteristic, these codes have been impossible to decode with good performance because, to reach high d_min, several encoding stages are connected through interleavers. This generates a large number of hidden variables and increases the complexity of the scheduling and initialization. However, the structure of the encoder is well suited for analog decoding. A proof‐of‐concept Cortex decoder for the (8, 4, 4) Hamming code is implemented in subthreshold 0.25‐μm CMOS. It outperforms an equivalent LDPC‐like decoder by 1 dB at BER=10^?5 and is 44 percent smaller and consumes 28 percent less energy per decoded bit.     

Design and Architecture of Low‐Latency High‐Speed Turbo Decoders

In this paper, we propose and present implementation results of a high‐speed turbo decoding algorithm. The latency caused by (de)interleaving and iterative decoding in a conventional maximum a posteriori turbo decoder can be dramatically reduced with the proposed design. The source of the latency reduction is from the combination of the radix‐4, center to top, parallel decoding, and early‐stop algorithms. This reduced latency enables the use of the turbo decoder as a forward error correction scheme in real‐time wireless communication services. The proposed scheme results in a slight degradation in bit error rate performance for large block sizes because the effective interleaver size in a radix‐4 implementation is reduced to half, relative to the conventional method. To prove the latency reduction, we implemented the proposed scheme on a field‐programmable gate array and compared its decoding speed with that of a conventional decoder. The results show an improvement of at least five fold for a single iteration of turbo decoding.     

An FPGA Implementation of High‐Speed Flexible 27‐Mbps 8‐StateTurbo Decoder

In this paper, we propose a flexible turbo decoding algorithm for a high order modulation scheme that uses a standard half‐rate turbo decoder designed for binary quadrature phase‐shift keying (B/QPSK) modulation. A transformation applied to the incoming I‐channel and Q‐channel symbols allows the use of an off‐the‐shelf B/QPSK turbo decoder without any modifications. Iterative codes such as turbo codes process the received symbols recursively to improve performance. As the number of iterations increases, the execution time and power consumption also increase. The proposed algorithm reduces the latency and power consumption by combination of the radix‐4, dual‐path processing, parallel decoding, and early‐stop algorithms. We implement the proposed scheme on a field‐programmable gate array and compare its decoding speed with that of a conventional decoder. The results show that the proposed flexible decoding algorithm is 6.4 times faster than the conventional scheme.     

Multistage Iterative Decoding With Complexity Reduction for Concatenated Space–Time Codes

Space–time encoders exploiting concatenated coding structures are efficient in attaining the high rates available to large-dimensional multiple-transmitter, multiple-receiver wireless systems under fading conditions, while also providing maximal diversity benefits. We present a multistage iterative decoding structure that takes full advantage of the concatenated nature of the transmission path, treating the modulator and channel stages as an additional encoder in serial concatenation. This iterative decoder architecture allows an encoder employing decoupled coding and modulation to reach the performance of coded modulation systems. It also admits reduced-complexity decoding with a computational load that is nonexponential in the number of antennas or the transmission bit rate, and makes practical decoding for large transmitter arrays possible. The performance curves for these methods follow the shape of the Fano bound, with only a modest power penalty.     

On the application of approximate APP decoding to digital videotransmission

For transmitting compressed digital video, the authors propose using threshold decodable block codes with large block length, and a posteriori probability (APP) soft decision decoding. A new approximation of the weight function associated with APP soft decision decoding of threshold decodable codes is presented. When the number of components in the parity equations is large, the new method gives excellent error performance, whereas there is a substantial degradation in the performance of the least reliable symbol approximation presented by Tanaka et al. (1980) and others. The effect of feedback on the performance of the APP decoder is also analyzed. It is shown that if the performance criterion is word error rate rather than bit error rate, feedback of previously decoded bits is essential to obtain all possible coding gain from the soft decision decoder. Finally, the performance of the proposed coding scheme is compared to the performance of a concatenated coding system with the same rate     

Hardware Implementation for Bipartite Belief Propagation Polar Decoding with Bit Flipping

For the scenarios with high throughput requirements, the belief propagation (BP) decoding is one of the most promising decoding strategies for polar codes. By pruning the redundant variable nodes (VNs) and check nodes (CNs) in the original factor graph, the graph is condensed to a sparse bipartite graph that is similar to the graph for low-density parity-check (LDPC) codes. In this paper, we introduce the bit flipping scheme into the LDPC-like BP (L-BP) decoding and propose two methods to identify the error-prone VNs. By additional decoding attempts, the L-BP flip (L-BPF) decoding improves the error-correction performance with a similar average complexity for high E_b/N₀ values. The simulation results show that the L-BPF decoding achieves 0.25 dB gain compared with the L-BP decoding. Finally, a parallel decoder with the proposed L-BPF algorithm for an (256,128) polar code is implemented using 65nm CMOS technology, and it delivers a throughput of 1877.3 Mbps.

     

Fast Multibit Decision Polar Decoder for Successive-Cancellation List Decoding

Successive-cancellation list (SCL) decoding for polar codes has the disadvantage of high latency owing to serial operations. To improve the latency, several algorithms with additional circuits have been proposed, but the area becomes larger. This paper proposes a fast multibit decision method having-high area efficiency based on the SCL decoding algorithm. First, multiple bits can be determined to reduce clock cycles using new nodes represented by the information bits and frozen bits. We propose the new nodes called the combined nodes and the other node in this paper. The combined nodes that combine redundant operations of the fast-simplified SC (fast-SSC) algorithm can increase area efficiency. The other node with bit patterns other than the node types of the fast-SSC algorithm performs an 8-bit multibit decision to reduce the number of decoding cycles. Latency is further reduced by applying a sphere decoding method to the other node. In addition, a sorter is proposed to reduce the critical path delay. As a large number of path metrics causes sorter delays, the proposed sorter can achieve high throughput with the small area. The proposed (1024, 512) SCL decoder showed negligible performance degradation in the simulation using Matlab and was synthesized using 65 nm CMOS technology. The proposed decoder achieves about 1.3Gbps with the small area. As a result, the area-throughput efficiency is at least 1.4 times higher than the state-of-the-art works over 1 Gbps.

     

A Reconfigurable TDMP Decoder for Raptor Codes

A Raptor code is a concatenation of a fixed rate precode and a Luby-Transform (LT) code that can be used as a rateless error-correcting code over communication channels. By definition, Raptor codes are characterized by irregularity features such as dynamic rate, check-degree variability, and joint coding, which make the design of hardware-efficient decoders a challenging task. In this paper, serial turbo decoding of architecture-aware Raptor codes is mapped into sequential row processing of a regular matrix by using a combination of code enhancements and architectural optimizations. The proposed mapping approach is based on three basic steps: (1) applying systematic permutations on the source matrix of the Raptor code, (2) confining LT random encoding to pseudo-random permutation of messages and periodic selection of row-splitting scenarios, and (3) developing a reconfigurable parallel check-node processor that attains a constant throughput while processing LT- and LDPC-nodes of varying degrees and count. The decoder scheduling is, thus, made simple and uniform across both LDPC and LT decoding. A serial decoder implementing the proposed approach was synthesized in 65 nm, 1.2 V CMOS technology. Hardware simulations show that the decoder, decoding a rate-0.4 code instance, achieves a throughput of 36 Mb/s at SNR of 1.5 dB, dissipates an average power of 27 mW and occupies an area of 0.55 mm².