W频段宽带倍频器

介绍了一个W频段宽带倍频器.采用反向并联二极管对结构实现宽带倍频.该倍频器输入为WR-28波导到微带过渡结构,输出为WR-10减高波导.在输入功率为5dBm时,在整个W频段输出功率为0.81±1.80dBm,二次谐波抑制度大于25dBc.该倍频器可把Ka频段的信号源扩展到W频段.     

Q波段宽带功率合成倍频器的设计北大核心CSCD

提出了一款输出频率覆盖整个Q波段的高功率固态有源四倍频器模块。倍频器基于混合集成电路技术实现,采用有源二倍频—功率放大—功率分配—无源二倍频—功率合成的拓扑结构。在前级采用基于悬置带线的180°反相器进行功分器设计,以实现宽带性能以及结构紧凑性。在无源二倍频时,采用两个分立的MA4E1310肖特基二极管组成非平衡倍频结构获取其二次谐波,并通过波导双探针进行合成输出,以此突破单个二极管的功率容量制约,进而提高倍频输出功率。测试结果表明,固态倍频源模块在5.5 V/0.9 A的直流偏置以及5 dBm的输入功率下,可以在33~50 GHz全波导频率范围内获得15~19 dBm的输出功率。     

基于肖特基势垒二极管三维电磁模型的220GHz三倍频器

采用阻性肖特基势垒二极管UMS DBES105a设计了一个太赫兹三倍频器.为了提高功率容量和倍频效率,该倍频器采用反向并联二极管对结构实现平衡式倍频.根据S参数测试曲线建立了该二极管的等效电路模型并提取了模型参数.由于在太赫兹频段二极管的封装影响到电路的场分布,将传统的二极管SPICE参数直接应用于太赫兹频段的电路设计存在一定缺陷,因此还建立了二极管的三维电磁模型.基于该模型研制出的220 GHz三倍频器最大输出功率为1.7 mW,最小倍频损耗为17.5 dB,在223.5 GHz~237 GHz输出频率范围内,倍频损耗小于22 dB.     

基于肖特基变容二极管的0.17 THz 二倍频器研制

研制了一种基于肖特基变容二极管的0.17 THz 二倍频器, 该器件为0.34 THz 无线通信系统收发前端提供了低相噪、低杂散的本振信号.倍频器结构基于波导腔体石英基片微带电路实现, 其核心器件是多结正向并联的肖特基变容二极管.文中采用结参数模型和三维电磁模型相结合的方式对二极管进行建模, 通过两种电路匹配方式实现了0.17 THz 二倍频器的最优化设计, 最终完成器件的加工及测试.测试结果表明, 在输入80~86 GHz, 20 dBm 的驱动信号下, 倍频器的最大输出功率达12.21 mW, 倍频效率11%, 输出频点为163 GHz;当前端输入功率达到饱和状态时, 该频点输出功率可达21.41 mW.     

基于肖特基阻性二极管的140 GHz二倍频器

介绍了一种基于肖特基阻性Z-极管的140GHzZ-倍频器,该倍频器采用矩形波导内嵌石英基片微带电路,通过四肖特基结正向并联结构提高驱动功率承受能力。倍频设计中应用了自建精确二极管三维电磁模型、宽带电磁耦合结构和宽带阻抗匹配结构,以提高仿真结果和实际器件的吻合度。测试结果表明：在频率为65GHz一75GHz,功率为20dBm的驱动信号激励下,二倍频器输出频率为130GHz～150GHz,输出功率为3．3dBm～8．0dBm,倍频损耗为11．7dB～16．3dB。在23dBm-24dBm的最大驱动功率激励下,倍频器最大输出功率达11．2dBm／136GHz,基本达到了成像雷达的应用性能指标。     

宽带毫米波四倍频器

对毫米波宽带四倍频器的设计方法并进行了理论分析及计算仿真。介绍了利用平衡式结构对奇次谐波进行抑制,从而实现宽带偶次倍频的原理,提出了选择肖特基二极管的原则。利用HFSS仿真和优化电路结构,采用微带线鳍线结构实现了宽频带的毫米波二倍频器。在此基础上,采用两级倍频的方式实现了宽带毫米波四倍频器。设计的Ka波段毫米波四倍频器输入频率6.625～10 GHz,输入功率为10 dBm时,在26.5～40 GHz频率范围内,输出功率大于10 dBm,对三次和五次谐波的抑制大于20 dBc。     

高功率110 GHz平衡式肖特基二极管频率倍频器

高频段的太赫兹信号通常是由多个倍频器级联输出的,因此要求倍频链路的前级必须具备高输出功率的能力。为了提升太赫兹倍频器的功率容量和效率,结合高频特性下肖特基二极管有源区电气模型建模方法,采用高热导率的陶瓷基片,利用对称边界条件,在HFSS和ADS中实现对倍频器电路的分析和优化,研制出了高功率110 GHz平衡式倍频器。最终测试结果表明,驱动功率为28 dBm左右时,该倍频器在102~114.2 GHz的工作带宽内的最高输出功率和效率分别为108 mW和17.6%,为链路后续的二倍频和三倍频提供足够的驱动功率。     

0.14 THz倍频器的设计与仿真

固态倍频器是毫米波及亚毫米波频段超外差接收机中的关键器件,其研制对太赫兹通信具有重要意义。介绍了一种基于肖特基变容二极管的宽带、高效率0.14 THz二倍频器的拓扑结构和仿真设计。该倍频器基于波导腔体石英基片微带电路形式,通过引线互联分别实现肖特基二极管接地和施加外部直流偏置,倍频器各部分采用了宽带电磁耦合结构设计。在开展了二极管建模及阻抗特性分析的基础上,采用三维有限元与非线性谐波平衡联合仿真方法,实现了倍频器的最优化设计。仿真结果表明,当输入频率为65 GHz~75 GHz,驱动功率为20 dBm时,倍频器的输出功率最高达10.1 dBm,倍频效率达10.8%。     

无基片空间合成的220 GHz三次倍频电路研究

基于四阳极结同向串联型GaAs平面肖特基二极管,设计并实现了无基片空间合成的220 GHz三次倍频电路。采用四支肖特基二极管协同工作,在脊波导小片上下两侧各倒装焊接两支肖特基二极管,构成上下反向结构。采用场路结合的方式,对倍频电路的倍频效率进行了仿真。仿真结果显示输入功率为300 mW,输出频率为213~229 GHz时,倍频效率大于3%;采用E波段功率放大器推动三次倍频电路,获得了倍频器输出功率。测试数据表明,驱动功率为300 mW时,输出频率为213~229 GHz时,输出功率大于5 dBm,倍频效率为1%~2%。     

W波段宽带倍频器的设计与仿真

本文介绍了一种由低次级联形式构成的W波段宽带六倍频器。输入信号先经过MMIC得到二倍频,再由反向并联二极管对平衡结构实现宽带三倍频,从而将Ku波段信号六倍频到W波段。该倍频器的输入端口为玻璃绝缘子同轴转换接头,输出为WR-10标准矩形波导结构。仿真结果表明当输入信号功率为20dBm时,三倍频器在整个W波段的输出三次谐波功率为4.5dBm左右,变频损耗小于17dB。该设计可以降低毫米波设备的主振频率,扩展已有微波信号源的工作频段。     

W波段功率合成六倍频源

通过倍频方法和功率合成方法设计了W波段六倍频源,将Ku或K波段信号倍频至W波段。信号经过Ka波段二倍频、巴仑、有源放大后,输出两路信号功率约为25 dBm,以此推动变容肖特基二极管进行三倍频,并进行功率合成输出。为了抑制偶次谐波和提高输出功率,二极管使用了反向并联平衡电路结构。该六倍频源在90-115 GHz 输出范围内输出功率大于12 dBm、最大输出功率为13.8 dBm、功率平坦度为1.2 dB。该模块提出了W波段源的产生方法,为今后设计W波段TR组件发射源提供了参考价值。     

Design of W-Band Tripler

This paper describes a high performance W-band tripler with a novel structure. Input frequency is 25-36.7 GHz, output frequency 75-110 GHz, input power is 20dBm and conversion loss 16 dB. It can extend microwave signal to W-band (adding in Ka-band doubler). In the design, we give some approaches to achieve high band performances.     

一种毫米波宽锁定范围的注入锁定倍频器设计

为提高毫米波段倍频器在低功耗下的工作带宽,采用IHP130 nm SiGe BiCMOS 工艺,设计了一种采用双端注入技术的毫米波宽锁定范围注入(DEI)锁定倍频器。该注入锁定倍频器主要由谐波发生器和带有尾电流源的振荡器构成,由巴伦产生差分信号双端注入振荡器的形式提高三次谐波注入强度,使其在E、W 等波段输出宽锁定范围和良好相位噪声性能的三倍频信号。仿真结果表明,注入锁定倍频器在工作电压为1.2 V,输入信号功率为0 dBm时,其锁定范围在57~105 GHz 内。在相同工作电压和输入信号功率下,输入频率为32 GHz 时,一次、二次和四次谐波抑制大于20 dBc,功耗为9.1 mW。     

A Broadband CMOS Frequency Tripler Using a Third-Harmonic Enhanced Technique

A third harmonic enhanced technique is proposed to implement a broadband and low-phase-noise CMOS frequency tripler. It nonlinearly combines a pair of differential fundamental signals to generate deep cuts at the peaks of the fundamental waveform, resulting in a strong third harmonic frequency output. This mechanism has inherent suppression on the fundamental and the other harmonics so that only a low-Q high-pass filter on the lossy silicon substrate is applied at the output to further reject the fundamental and the second harmonic frequencies, in contrast to the high-Q filters used in most of the previous tripler designs. The fabricated circuit using 0.18 m CMOS technology is compact and has an input frequency range from 1.7 GHz to 2.25 GHz, or an output frequency range from 5.1 GHz to 6.75 GHz, resulting in about 28% frequency bandwidth. The optimum conversion loss from the tripler is 5.6 dB (27.5% efficiency) at an input power of 2 dBm. The suppressions for the fundamental, second and fourth harmonics in the measurement are better than 11 dB, 9 dB, and 20 dB within an input power range from 2 dBm to 7 dBm.     

Novel design for small-size coplanar waveguide frequency tripler

This letter presents a novel design for a small-size coplanar waveguide frequency tripler. In this study, a new BPF has been replaced the conventional stub lines in the output termination of the multiplier. Not only enhance the performance of the tripler, but also reduce the whole circuit size. to 2.125/spl times/2.275 cm/sup 2/ in the frequency 0.8/2.4 GHz, The spurious suppressions are 37.48, 33.38, and 32.08 dBc for the 1st, 2nd, and 4th harmonics, respectively. It reveals the best output power of -1.92 dBm for a 0 dBm input signal and maximum conversion gain of -1.92 dB. It is very useful for applications in the wireless communication and radar systems.     

G-band metamorphic HEMT-based frequency multipliers

Two monolithic G-band active frequency multipliers have been designed and fabricated using coplanar-waveguide technology. The monolithic microwave integrated circuits are a frequency tripler for an output frequency of 140 GHz and a 110-220-GHz frequency doubler. The tripler demonstrates a maximum conversion gain of -11 dB for an input power of 9 dBm, whereas the doubler achieves a conversion gain of -7 dB for a 2.5-dBm input signal. The circuits have been realized using two InAlAs/InGaAs-based metamorphic high electron-mobility transistor processes with different gate lengths of 100 and 50 nm, respectively.     

Design of a W-band Frequency Tripler for Broadband Operation Based on a Modified Equivalent Circuit Model of GaAs Schottky Varistor Diode

This paper presents the design and experimental results of a W-band frequency tripler with commercially available planar Schottky varistor diodes DBES105a fabricated by UMS, Inc. The frequency tripler features the characteristics of tunerless, passive, low conversion loss, broadband and compact. Considering actual circuit structure, especially the effect of ambient channel around the diode at millimeter wavelength, a modified equivalent circuit model for the Schottky diode is developed. The accuracy of the magnitude and phase of S21 of the proposed equivalent circuit model is improved by this modification. Input and output embedding circuits are designed and optimized according to the corresponding embedding impedances of the modified circuit model of the diode. The circuit of the frequency tripler is fabricated on RT/Rogers 5880 substrate with thickness of 0.127 mm. Measured conversion loss of the frequency tripler is 14.5 dB with variation of ±1 dB across the 75?~?103 GHz band and 15.5?~?19 dB over the frequency range of 103?~?110 GHz when driven with an input power of 18 dBm. A recorded maximum output power of 6.8 dBm is achieved at 94 GHz at room temperature. The minimum harmonics suppression is greater than 12dBc over 75?~?110 GHz band.     

225–255-GHz InP DHBT Frequency Tripler MMIC Using Complementary Split-Ring Resonator

In this paper, a novel design of frequency tripler monolithic microwave integrated circuit (MMIC) using complementary split-ring resonator (CSRR) is proposed based on 0.5-μm InP DHBT process. The CSRR-loaded microstrip structure is integrated in the tripler as a part of impedance matching network to suppress the fundamental harmonic, and another frequency tripler based on conventional band-pass filter is presented for comparison. The frequency tripler based on CSRR-loaded microstrip generates an output power between ?8 and ?4 dBm from 228 to 255 GHz when the input power is 6 dBm. The suppression of fundamental harmonic is better than 20 dBc at 77–82 GHz input frequency within only 0.15?×?0.15 mm² chip area of the CSRR structure on the ground layer. Compared with the frequency tripler based on band-pass filter, the tripler using CSRR-loaded microstrip obtains a similar suppression level of unwanted harmonics and higher conversion gain within a much smaller chip area. To our best knowledge, it is the first time that CSRR is used for harmonic suppression of frequency multiplier at such high frequency band.     

110GHz 阻性平衡三倍频器设计

本文介绍了一种基于阻性肖特基二极管芯片UMS DBES105a 的110GHz 三倍频器,通过两个芯片反向并联形成 了平衡结构,同时提高了倍频器的功率承受能力。电路设计中使用二极管三维电磁模型,匹配设计时未设计专门的输入 过渡和滤波器,而是直接经行匹配设计,提供了更多的可优化参量,以达到最佳的匹配效果和带宽。经过HFSS 和ADS 联合仿真,在频率为31~44GHz,功率为20dBm 的驱动信号激励下,三倍频器输出频率大于7dBm,最大输出功率为 9.1dBm@105GHz。