三值钟控绝热静态随机存储器设计

通过对多值逻辑、绝热电路和三值SRAM结构的研究,提出一种新颖的三值钟控绝热静态随机存储器(SRAM)的设计方案。该方案利用NMOS管的自举效应,以绝热方式对SRAM的行列地址译码器、存储单元、敏感放大器等进行充放电,有效恢复储存在字线、位线、行列地址译码器等大开关电容上的电荷,实现三值信号的读出写入和能量回收。PSPICE模拟结果表明,所设计的三值钟控绝热SRAM具有正确的逻辑功能和低功耗特性,在相同的参数和输入信号情况下,与三值常规SRAM相比,节约功耗达68%。     

钟控传输门绝热逻辑电路和SRAM的设计

本文利用NMOS管的自举效应设计了一种新的采用二相无交叠功率时钟的绝热逻辑电路——钟控传输门绝热逻辑电路,实现对输出负载全绝热方式充放电.依此进一步设计了一种新型绝热SRAM,从而可以以全绝热方式有效恢复在字线、写位线、敏感放大线及地址译码器上的大开关电容的电荷.最后,在采用TSMC 0.25 μ m CMOS工艺器件参数情况下,对所设计的绝热SRAM进行HSPCIE模拟,结果表明,此SRAM逻辑功能正确,低功耗特性明显.     

A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing

A 2 muW, 100 kHz, 480 kb subthreshold SRAM operating at 0.2 V is demonstrated in a 130 nm CMOS process. A 10-T SRAM cell allows 1 k cells per bitline by eliminating the data-dependent bitline leakage. A virtual ground replica scheme is proposed for logic "0" level tracking and optimal sensing margin in read buffers. Utilizing the strong reverse short channel effect in the subthreshold region improves cell writability and row decoder performance due to the increased current drivability at a longer channel length. The sizing method leads to an equivalent write wordline voltage boost of 70 mV and a delay improvement of 28% in the row decoder compared to the conventional sizing scheme at 0.2 V. A bitline writeback scheme was used to eliminate the pseudo-write problem in unselected columns.     

A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM

An ultrahigh-speed 4.5-Mb CMOS SRAM with 1.8-ns clock-access time, 1.8-ns cycle time, and 9.84-μm² memory cells has been developed using 0.25-μm CMOS technology. Three key circuit techniques for achieving this high speed are a decoder using source-coupled-logic (SCL) circuits combined with reset circuits, a sense amplifier with nMOS source followers, and a sense-amplifier activation-pulse generator that uses a duplicate memory-cell array. The proposed decoder can reduce the delay time between the address input and the word-line signal of the 4.5-Mb SRAM to 68% of that of an SRAM with conventional circuits. The sense amplifier with nMOS source followers can reduce not only the delay time of the sense amplifier but also the power dissipation. In the SRAM, the sense-amplifier activation pulse must be input into the sense amplifier after the signal from the memory cell is input into the sense amplifier. A large timing margin required between these signals results in a large access time in the conventional SRAM. The sense-amplifier activation pulse generator that uses a duplicate memory-cell array can reduce the required timing margin to less than half of the conventional margin. These three techniques are especially useful for realizing ultrahigh-speed SRAM's, which will be used as on-chip or off-chip cache memories in processor systems     

Design and process variation analysis of CNTFET-based ternary memory cells

Two novel ternary CNTFET-based SRAM cells are proposed in this paper. The first proposed CNTFET SRAM uses additional CNTFETs to sink the bit lines to ground; its operation is nearly independent of the ternary values. The second cell utilizes the traditional voltage controller (or supply) of a binary SRAM in a ternary SRAM; it consists of adding two CNTFETs to the first proposed cell. CNTFET features (such as sizing and density) and performance metrics (such as SNM and PDP) and write/read times are considered and assessed in detail. The impact of different features (such as chirality and CNT density) is also analyzed with respect to the operations of the memory cells. The effects of different process variations (such as lithography and density/number of CNTs) are extensively evaluated with respect to performance metrics. In nearly all cases, the proposed cells outperform existing CNTFET-based cells by showing a small standard deviation in the simulated memory circuits.     

25.6 Gbit/s horizontally and vertically accessible embeddedmultiport SRAM

An architecture for an embedded 8-port SRAM with 256 bit simultaneous horizontal and vertical data access for adjacent or alternate addresses is proposed. This architecture makes possible four kinds of address configurations which are effective in video applications by selecting multiple word lines and one of four bit lines for each column multiplexer. The proposed SRAM provides 25.6 Gbit/s of high bandwidth     

An 8 ns 4 Mb serial access memory

A new architecture for serial access memory is described that enables a static random access memory (SRAM) to operate in a serial access mode. The design target is to access all memory address serially from any starting address with an access time of less than 10 ns. This can be done by all initializing procedure and three new circuit techniques. The initializing procedure is introduced to start the serial operation at an arbitrary memory address. Three circuit techniques eliminate extra delay time caused by an internal addressing of column lines, sense amplifiers, word lines, and memory cell blocks. This architecture was successfully implemented in a 4-Mb CMOS SRAM using a 0.6 μm CMOS process technology. The measured serial access time was 8 ns at a single power supply voltage of 3.3 V     

High speed IP address lookup architecture using hashing

One of the most important design issues for IP routers responsible for datagram forwarding in computer networks is the route-lookup mechanism. In this letter, we explore a practical IP address lookup scheme which converts the longest prefix matching problem into the exact matching problem. In the proposed architecture, the forwarding table is composed of multiple SRAM, and each SRAM represents an address lookup table in a single prefix. Hashing functions are applied to each address lookup table in order to find out matching entries in parallel, and the entry matched with the longest prefix among them is selected. Simulation using data from the MAE-WEST router shows that a large routing table with 37000 entries is compacted to a forwarding table of 189 kbytes in the proposed scheme and achieves one route lookup every two memory accesses in average.     

SRAM版图布局方向对产品失效率的影响

静态随机存储器(SRAM)是集成电路中重要的存储结构单元。由于其制备工艺复杂、关键尺寸较小、对设计规则的要求最为严格,因此SRAM的质量是影响芯片良率的关键因素。针对一款微控制单元(MCU)芯片的SRAM失效问题,进行逻辑地址分析确认失效位点,通过离子聚焦束(FIB)切片及扫描电子显微镜(SEM)分析造成失效的异常物理结构,结合平台同类产品的设计布局对比及生产过程中光刻工艺制程的特点,确认失效的具体原因。对可能造成失效的工艺步骤或参数设计实验验证方案,根据验证结果制定相应的改善措施,通过良率测试及SEM照片确认改善结果,优化工艺窗口。当SRAM中多晶硅线布局方向与测试单元中一致时,工艺窗口最大,良率稳定;因此在芯片设计规则中明确SRAM结构布局方向,对于保证产品的良率具有重要意义。     

A low leakage SRAM macro with replica cell biasing scheme

For mobile applications of SRAMs, there is a need to reduce standby current leakages while keeping memory cell data. For this purpose, we propose a replica cell biasing scheme which controls the cell bias voltage by self-tuning using replica cells. This scheme minimizes the cell leakage regardless of the process fluctuations and the environmental conditions. In addition, leakage reduction in row decoder circuits is also desirable, because standby current leakages in peripheral circuits are dominated by row decoders. We also propose a row decoder circuit which can reduce both the off-leakage and the gate-leakage in the row decoders. We fabricated a 90-nm 512-Kb low-leakage SRAM macro to verify the proposed leakage reduction techniques. With these techniques, 88% reduction of the standby leakage in the sleep mode and 40% reduction of the leakage compared with the conventional diode clamp scheme are realized.     

一种基于全数字锁相环的SRAM实速测试方案

提出了一种采用实速测试方式测试SRAM性能参数及可靠性的方案。该方案在内建自测试(BIST)电路的基础上,通过增加一个超高速ADPLL为SRAM性能的实速测试提供一个高频时钟,同时还加入延时链来产生不同相位的4个时钟。通过调整这4个时钟的相位来获得SRAM的关键性能参数,如存取时间、地址建立和保持时间等。该方案在UMC 55nm CMOS标准逻辑工艺下流片验证。测试结果显示,SRAM最大测试工作频率约为1.3GHz,测试精度为35ps。     

A low standby-power fast carbon nanotube ternary SRAM cell with improved stability

Power dissipation,speed and stability are the most important parameters for multiple-valued SRAM design.To reduce the power consumption and further improve the performance of the ternary SRAM cell,we propose a low standby-power fast ternary SRAM cell based on carbon nanotube field effect transistors (CNFETs).The performance is simulated in terms of three criteria including standby-power,delay (write and read) and stability (RSNM).Compared to the novel ternary SRAM cell,our results show that the average standby-power,write and read delay of the proposed cell are reduced by 78.1％,39.6％ and 58.2％,respectively.In addition,the RSNM under process variations is 2.01 × and 1.95× of the conventional and novel ternary SRAM cells,respectively.     

Wire Optimization and Delay Reduction for High‐Performance on‐Chip Interconnection in GALS Systems

To address the wire complexity problem in large‐scale globally asynchronous, locally synchronous systems, a current‐mode ternary encoding scheme was devised for a two‐phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current‐mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current‐mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using 0.25‐μm CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10‐mm wire. They also reduce the power‐delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.     

A 1 ns, 1 W, 2.5 V, 32 Kb NTL-CMOS SRAM macro using a memory cellwith PMOS access transistors

While an ECL-CMOS SRAM can achieve both ultra high speed and high density, it consumes a lot of power and cannot be applied to low power supply voltage applications. This paper describes an NTL (Non Threshold Logic)-CMOS SRAM macro that consists of a PMOS access transistor CMOS memory cell, an NTL decoder with an on-chip voltage generator, and an automatic bit line signal voltage swing controller. A 32 Kb SRAM macro, which achieves a 1 ns access time at 2.5 V power supply and consumes a mere 1 W, has been developed on a 0.4 μm BiCMOS technology     

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an accesstime of 550 ps and an operating frequency of 900 MHz

This paper describes power reduction circuit techniques in an ultra-high-speed emitter-coupled logic (ECL)-CMOS SRAM. Introduction of a 0.25-μm MOS transistor allows a Y decoder and a bit-line driver to be composed of CMOS circuits, resulting in a power reduction of 34%. Moreover, a variable-impedance load has been proposed to reduce cycle time. A 1-Mb ECL-CMOS SRAM was developed by using these circuit techniques and 0.2-μm BiCMOS technology. The fabricated SRAM has an ultrafast access time of 550 ps and a high operating frequency of 900 MHz with a power dissipation of 43 W     

维特比译码器的路径度量存储更新方法

采用一种新的方法较好地解决了维特比译码器的路径度量存储更新问题,详细介绍了状态地址的映射、加比选(ACS)单元计算顺序的调度、地址产生器的设计,并给出一个64状态8个ACS的维特比译码器的度量存储更新的实例,该方法具有互联面积小、控制逻辑简单和硬件资源消耗少的特点。     

X-Calibration: A Technique for Combating Excessive Bitline Leakage Current in Nanometer SRAM Designs

In an SRAM circuit, the leakage currents on the bit lines are getting increasingly prominent with the dwindling of transistors' threshold voltages as the technology scales down to 90 nm and beyond. Excessive bit-line leakage current results in slower read operations or even functional failure. In this paper, we present a new technique, called X-calibration, to combat this phenomenon. Unlike the previous method that attempts to compensate the leakage current directly, this scheme first transforms the bit-line leakage current into an equilibrium offset voltage across the bit-line pair, and then simple circuitry is utilized to cancel this offset accurately at the input of the sense amplifier so that the sensing is not affected by the bit-line leakage. SPICE simulation of a 1 Kbit SRAM macro shows that this X-calibration scheme can handle 83% higher bit-line leakage current than the previous bit-line leakage compensation scheme. Measurement results of the test chip show that the SRAM macro adopting X-calibration scheme can cope with up to 320 $mu{hbox{A}}$ bit-line leakage current.      

低功耗绝热SRAM

文章提出了一种新的绝热电路,并以该绝热电路为驱动,设计了一种低功耗绝热SRAM.由于所提出的绝热电路能以完全绝热的方式回收位线和字线上大开关电容的电荷,因此使该SRAM的功耗大大减小.我们采用0.25μm TSMC工艺,在时钟频率25～200MHz范围内对绝热SRAM进行了能耗和功能的HSPICE仿真,结果显示,与用传统的CMOS电路设计的SRAM相比,可节能80%左右.     

一种512 Kbit同步高速SRAM的设计

设计了一种深亚微米 ,单片集成的 5 1 2 K( 1 6K× 32位 )高速静态存储器 ( SRAM)。该存储器可以作为IP核集成在片上系统中。存储器采用六管 CMOS存储单元、锁存器型敏感放大器和高速译码电路 ,以期达到最快的存取时间。该存储器用 0 .2 5μm五层金属单层多晶 N阱 CMOS工艺实现 ,芯片大小为 4.8mm× 3.8mm。测试结果表明 ,在 1 0 MHz的工作频率下 ,存储器的存取时间为 8ns,工作电流 7m A。     

Fast Tag Comparator Using Diode Partitioned Domino for 64-bit Microprocessors

As the clock frequency and physical address space of 64-bit microprocessors continue to grow, one major critical path is the access to the on-die cache memory that includes a tag comparator, a tag SRAM and a data SRAM. To improve the delay of the tag comparator, a diode-partitioned (DP) domino circuit is proposed. DP domino reduces the parasitic capacitance and enables a smaller keeper in high fan-in gates. The diode circuit is also improved by an enhanced diode that boosts up the gate voltage of the nMOS diode. Delay of a 40-bit tag comparator using the proposed scheme is 33% faster than an optimized complex domino circuit in 1.8-V 180-nm CMOS technology