量子隧穿效应“孵出”能效更高的隧穿晶体管

据报道,美国圣母大学和宾夕法尼亚州立大学的科学家们表示,他们借用量子隧穿效应,研制出了性能可与目前的晶体管相媲美的隧穿场效应晶体管（TFET）。最新技术有望解决目前芯片上的晶体管生热过多的问题,在一块芯片上集成更多的晶体管,从而提高电子设备的计算能力。晶体管是电子设备的基本组成元件,在过去的40年间,科学家们主要通过将更多的晶体管集成到一块芯片上来提高电子设备的计算能力,但目前这条道路似乎已快走到尽头。业界认为,半导体工业正在快速地接近晶体管小型化的物理极限,现代晶体管的主要问题是产生过多的热量。     

隧穿场效应晶体管的特性分析

随着器件尺寸不断缩小,半导体器件面临诸多问题,如短沟道效应严重、泄露电流大、高功耗等,针对这些问题,领域内提出了各种解决方案,其中隧道场效应晶体管得到广泛关注,它是一种新型的低功耗器件,其阈值泄露小,可抗短沟道效应.本文以隧穿场效应晶体管的工作原理、影响器件性能的因素和发展概况为着眼点,简析该新型器件.     

量子隧穿效应“孵出”能效更高的隧穿晶体管 有望解决目前芯片上晶体管生热过多的问题

<正>据美国物理学家组织网3月27日(北京时间)报道,美国圣母大学和宾夕法尼亚州立大学的科学家们表示,他们借用量子隧穿效应,研制出了性能可与目前的晶体管相媲美的隧穿场效应晶体管(TFET)。最新     

一种感应PN结隧穿场效应晶体管

提出了一种在源区形成感应PN结的隧穿场效应晶体管,利用Silvaco TCAD对器件的工作原理进行了验证,并仿真分析了器件的静态电学特性以及动态特性。结果表明,这种结构的TFET具有低的亚阈值斜率(51mV/dec.)、高的开态电流(5.88μA/μm)、高的开/关态电流比(ION/IOFF为107)以及低至9ps的本征延迟时间,表明利用该结构的TFET器件有望构成高速低功耗逻辑单元。     

一种新型隧穿场效应晶体管

提出了一种新型隧穿场效应晶体管(TFET)结构,该结构通过在常规TFET靠近器件栅氧化层一侧的漏-体结界面引入一薄层二氧化硅(隔离区),从而减小甚至阻断反向栅压情况下漏端到体端的带带隧穿(BTBT),减弱TFET的双极效应,实现大幅度降低器件泄漏电流的目的。利用TCAD仿真工具对基于部分耗尽绝缘体上硅(PDSOI)和全耗尽绝缘体上硅(FDSOI)的TFET和新型TFET结构进行了仿真与对比。仿真结果表明,当隔离区宽度为2 nm,高度大于10 nm时,可阻断PDSOI TFET的BTBT,其泄漏电流下降了4个数量级;而基于FDSOI的TFET无法彻底消除BTBT和双极效应,其泄漏电流下降了2个数量级。因此新型结构更适合于PDSOI TFET。     

英飞凌在IEDM展示新型穿隧式场效应晶体管

2004年12月13-15日，在美国旧金山举行的2004年IEEE国际电子器件会议(IEDM)上，英飞凌科技公司(Infineon Technologies)的科学家宣读了几份论文，展示了他们取得的成果。英飞凌和德国慕尼黑科技大学共同提出了一种适用于制造低压数字和模拟电路的可伸缩性晶体管概念。现在，人们终于可以将互补穿隧式场效应晶体管(TFET)用于标准硅工艺，制造出具备出色静态和动态性能的芯片。     

粗糙界面对超薄栅MOS结构的直接隧穿电流的影响

研究了粗糙界面对电子隧穿超薄栅金属 -氧化物 -半导体场效应晶体管的氧化层的影响 .对于栅厚为 3nm的超薄栅 MOS结构的界面用高斯粗糙面进行模拟来获取界面粗糙度对直接隧穿电流的影响 ,数值模拟的结果表明 :界面粗糙度对电子的直接隧穿有较大的影响 ,且直接隧穿电流随界面的粗糙度增加而增大 ,界面粗糙度对电子的直接隧穿的影响随着外加电压的增加而减小 .     

粗糙界面对超薄栅MOS结构的直接隧穿电流的影响

研究了粗糙界面对电子隧穿超薄栅金属-氧化物-半导体场效应晶体管的氧化层的影响.对于栅厚为3nm的超薄栅MOS结构的界面用高斯粗糙面进行模拟来获取界面粗糙度对直接隧穿电流的影响,数值模拟的结果表明:界面粗糙度对电子的直接隧穿有较大的影响,且直接隧穿电流随界面的粗糙度增加而增大,界面粗糙度对电子的直接隧穿的影响随着外加电压的增加而减小.     

耦合双量子点中基态电子的隧穿特性

介绍了以Si/SiO2系统构成的量子异或门的工作原理,研究了耦合不对称双量子点所构成的量子比特的电子隧穿特性.研究结果表明,通过栅压可很好地实现控制电子在两个量子点间共振隧穿,其隧穿时间随势垒厚度和量子点尺寸结构参数发生显著的变化.目前模拟的特征变化曲线表明,可获得实验上理想的隧穿时间(工作频率)和相应的栅压(工作电压).     

耦合双量子点中基态电子的隧穿特性

介绍了以Si/SiO2系统构成的量子异或门的工作原理,研究了耦合不对称双量子点所构成的量子比特的电子隧穿特性.研究结果表明,通过栅压可很好地实现控制电子在两个量子点间共振隧穿,其隧穿时间随势垒厚度和量子点尺寸结构参数发生显著的变化.目前模拟的特征变化曲线表明,可获得实验上理想的隧穿时间(工作频率)和相应的栅压(工作电压).     

Germanium vertical Tunneling Field-Effect Transistor

The first realization of a pure Germanium bulk vertical Tunneling Field-Effect Transistor (vTFET) and a high I_on/I_off ratio for a pure Silicon bulk vTFET are both reported. The manufacturing process, the electrical characteristics and key features and the differences of the two varieties of vTFET devices (pure Germanium bulk vTFET and pure Silicon bulk vTFET) will be discussed in detail.     

一种带有斜向扩展源的双栅隧穿场效应晶体管

设计并研究了一种带有轻掺杂漏(LDD)和斜向扩展源(OES)的双栅隧穿场效应晶体管(DG-TFET),并利用Sentaurus TCAD仿真工具对栅长及扩展源长度等关键参数进行了仿真分析。对比了该器件与传统TFET的亚阈值摆幅、关态电流和开关电流比,并从器件的带带隧穿概率分析其优势。仿真结果表明,该器件的最佳数值开关电流比及亚阈值摆幅分别可达3.56×10¹²和24.5 mV/dec。另外,该DG-TFET在双极性电流和接触电阻方面性能良好,且具有较快的转换速率和较低的功耗。     

量子电子器件——谐振隧道晶体管(RTT)

本文介绍了RTT的概念和谐振隧穿双势垒(DB)的理论,综述了RTT的最新进展,其中包括基区和发射区内有DB的谐振隧道双极晶体管(RTBT)、多态RTBT、超晶格RTBT、双极量子RTT(BiQuaRTT)和单极量子线RTT。     

Correction to “Revision of Tunneling Field-Effect Transistor in Standard CMOS Technologies”

Previously published results by the authors, from 2004 to 2006, on the tunneling field-effect transistor (TFET) are revised in this correction. The devices that they had characterized as TFETs contain a conducting path in parallel to the intended tunneling junction. Therefore, the measured characteristics are similar to a MOSFET with a resistive source connection     

量子电子器件——谐振隧道热电子晶体管(RHET)

RHET是一种新型高速功能器件,在这种器件中,电子谐振隧穿量子阱谐振隧道势垒(RTB)从发射极注入到基极中,然后以准弹道方式传输到收集极。其主要特点是,高速的电荷传输和宽的负微分电阻。本文综述了RHET的研究与进展,并介绍了采用RHET构成的集成电路。     

VDMOS场效应晶体管的研究与进展

介绍了新一代电力电子器件VDMOS的发展概况及工作原理，分析了其技术特点与优势，重点阐述了近年来国际上VDMOS在高压大电流及低压大电流方面所取得的理论及技术突破，通过不断改进的沟槽技术以及封装工艺提高了器件的整体性能，而Superjunction新结构、SiC新材料的采用突破了Si的高压应用理论极限。最后对未来的研究方向作了展望。     

A Semianalytical Model of Bilayer-Graphene Field-Effect Transistor

Bilayer graphene has the very interesting property of an energy gap tunable with the vertical electric field. We propose an analytical model for a bilayer-graphene field-effect transistor, suitable for exploring the design parameter space in order to design a device structure with promising performance in terms of transistor operation. Our model, based on the effective mass approximation and ballistic transport assumptions, takes into account bilayer-graphene tunable gap and self-polarization and includes all band-to-band tunneling current components, which are shown to represent the major limitation to transistor operation, because the achievable energy gap is not sufficient to obtain a large $I_{rm on}/I_{rm off}$ ratio.      

Design and Characteristics of the Lightly Doped Drain-Source (LDD) Insulated Gate Field-Effect Transistor

The LDD structure, where narrow, self-aligned n/sup -/ regions are introduced between the channel and the n/sup +/ source-drain diffusions of an IGFET to spread the high field at the drain pinchoff region and thus reduce the maximum field intensity, is analyzed. The design is shown, including optimization of then- dimensions and concentrations and the boron channel doping profile and an evaluation of the effect of the series resistance of the n- regions on device transconductance. Characteristics of experimental devices are presented and compared to those of conventional IGFET's. It is shown that significant improvements in breakdown voltages, hot-electron effects, and short-channel threshold effects can be achieved allowing operation at higher voltage, e.g., 8.5 versus 5 V, with shorter source-drain spacings, e.g., 1.2 versus 1.5 /spl mu/m. Alternatively, a shorter channel length could be used for a given supply voltage. Performance projections are shown which predict 1.7 X basic device/circuit speed enhancement over conventional structures. Due to the higher voltages and higher frequency operation, the higher performance results in an increase in power which must be considered in a practical design.     

Threshold-Voltage Fluctuation of Double-Gated Poly-Si Nanowire Field-Effect Transistor

In this letter, the fluctuation characteristics of polycrystalline silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) with independently controlled double-gate configuration were studied. The defects existing in the NW channels are identified as one of the major sources for the fluctuation. The passivation of these defects by plasma treatment is shown to be effective for reducing the fluctuation. We have also found that the fluctuation is closely related to the operation modes. When only one of the gates is employed as the driving gate to control the switching behavior of the device, an optimum bias for the other gate can be found for minimizing the fluctuation.      

Influence of Block Oxide Width on a Silicon-on-Partial-Insulator Field-Effect Transistor

In this paper, the influence of block oxide width (W_BO) variations on a newly designed 40-nm gate-length silicon-on-partial-insulator field-effect transistor with block oxide (bSPIFET) was demonstrated and characterized. By utilizing the block oxide (BO) enclosing the sidewall of the Si body, the charge sharing from the source/drain (S/D) regions for a bSPIFET can be significantly reduced. Essentially, because the BO is adopted for a bSPIFET, its ultrashort-channel characteristics are similar to an ultrathin-body silicon-on-insulator (UTBSOI), although it possesses a thicker S/D region than a UTBSOI. From the simulation tests, it was also found that although the wider BO can suppress the ultrashort-channel effects (USCEs), the drain ON-state current I_ON slightly decreases because certain areas of the S/D are occupied by BO. Despite this problem, the bSPIFET still exhibits a good USCE control and a high-drive current. In addition, the self-heating effects are also ameliorated as a result of the natural body-tied scheme.