X波段频率综合器锁相环相位噪声特性分析

本文分析了某雷达频综3cm锁相环的噪声特性。计算出了锁相环输出相噪的理论值。并对影响输出相位噪声的主要因素做了分析。最后给出了试验结果。     

一种超低相位噪声宽带频率合成器的设计

基于对双环频率预置技术和谐波混频技术的理论分析,将混频锁相合成方式与高次倍频合成方式相结合,采用鉴相极性可变的非常规设计,提出一种宽带小步进超低相位噪声频率合成器的低成本实现方案,并对合成器的相位噪声和杂散抑制指标进行了理论分析。试验证明,在8 GHz输出频率下,方案实现了低于-132 d Bc/Hz@10 k Hz的相位噪声和70 d B以上的杂散抑制性能。对宽带超低相位噪声频率合成器的设计具有借鉴意义。     

K波段低相位噪声频率综合器的设计与实现

采用双锁相环混频设计方案,设计了一种低相位噪声频率综合器,实现了单锁相环难以实现的低相位噪声指标。在系统理论分析的基础上,优化了电路布局,实际的电路尺寸为45.0 mm×30.0 mm×12.0 mm,实现了小型化K波段低相位噪声频率综合器。对频率综合器电路进行了测试,输出信号相位噪声为 -95 dBc/Hz @1 kHz和 -99 dBc/Hz @≥40 kHz,杂散为-72 dBc,完全满足设计指标的要求。     

一种超低相噪参考源的设计与实现

本文设计并实现了超低相位噪声参考源.分析了锁相频率合成相位噪声的影响因素,提出了一种采用梳谱发生器合成宽带、大步进、超低噪声参考源的频率合成方案.实验测试结果:频率覆盖范围3~6GHz,频率步进75MHz,3.1125GHz时,10kHz频偏处的相位噪声约为-130dBc/Hz,具有较高的工程实用价值.     

一种低附加相位噪声的频率合成方法

频率源的相位噪声水平直接制约雷达的性能上限,因而低相噪频率合成技术是高性能雷达系统的一项关键技术。现有低相噪频率合成方法常用高次倍频实现,整体性能上严重依赖于低相噪晶振,成本一直居高不下。对此,提出一种低附加相位噪声频率合成方法,即采用最小化链路上附加相位噪声的技术,用普通恒温晶振级联低相噪放大器、梳状谱发生器和锁相环,最终实现低相位噪声的频率合成。实测数据表明,本文方法以100 MHz普通恒温晶振为参考,积分区间[1 kHz, 30 MHz]的时间抖动为11 fs,频率合成在5.8 GHz载波的相位噪声为-119 dBc/Hz@1 kHz,积分区间[1 kHz, 30 MHz]的时间抖动为13.7 fs,总附加时间抖动为8.17 fs,附加相位噪声仅1.9 dB,达到了业界领先水平,能够有效提升毫米波雷达系统的成像性能,优于传统频率合成方法。     

数字化频率综合器的相位噪声分析与估算

利用随机过程理论计算了数字化频率综合器中各个量化噪声，并在假设各等效量化噪声相互独立前提下得出了输出相位噪声值，同时给出在不同采样率和不同数字电路精度情况下输出相位噪声变化，并得出了一般性结论。     

超低相位噪声快速宽带频率合成器的研究

本文介绍了一种快速、高分辨力、低相、低杂散的频率合成器方案,该方案采用DDS＋PLL合成方法，通过大幅度降低环路内的分频比来改善相位噪声指标，同时采用加动态预制电压的方法来提高环路转换时间。实践证明该方案是成功的，达到的主要技术指标为：相位噪声≤-112dBc/Hz @ 10kHz,杂散≤-70dBc，步进间隔10Hz，转换速度＜100μs。     

锁相环频率合成器相位噪声分析

频率合成器的相位噪声直接影响动目标雷达的改善因子。本文着重对锁相环频率合成器的相位噪声进行了较全面的分析，并对其中各组成部件的相位噪声也做了分析，分析的结果与实际测量结果基本吻合。文中最后提出了改善ＰＬＬ频率合成器相位噪声的办法。     

一种2.4GHz正交输出频率综合器

介绍了一种用于bluetooth的基于0.35μm CMOS工艺的2.4GHz正交输出频率综合器的设计和实现.采用差分控制正交耦合压控振荡器实现I/Q信号的产生.为了降低应用成本,利用一个二阶环路滤波器以及一个单位增益跨导放大器来代替三阶环路滤波器.频率综合器的相位噪声为-106.15dBc/Hz@1MHz,带内相位噪声小于-70dBc/Hz,3.3V电源下频率综合器的功耗为13.5mA,芯片面积为1.3mm×0.8mm.     

An ultra-low power integer-N frequency synthesizer for MICS transceivers

The ultra-low power frequency synthesizer for the transceivers used in the application of Medical Implantable Communication Services (MICS) is presented. The MICS band is from 402 to 405 MHz. Each channel spacing is 300 kHz. Integer-N architecture is used to implement the frequency synthesizer. The post layout simulations show that the total power consumption of the system is less than at 1.2 V power supply. The gains of the charge pump and voltage controlled oscillator (VCO) are and 50 MHz/V, respectively. The standard 300 kHz external clock is used as the reference. The design is carried out in the IBM 90 nm 9LPRF CMOS technology.     

一种宽带低相噪频率合成器的设计方法研究

提出了一种宽带低相噪频率合成器的设计方法.采用了数字锁相技术,该锁相技术主要由锁相环（phase locked loop,PLL）芯片、有源环路滤波器、宽带压控振荡器和外置宽带分频器等构成,实现了10~20 GHz范围内任意频率输出,具有输出频率宽、相位噪声低、集成度高、功耗低和成本低等优点.最后对该PLL电路杂散抑制和相位噪声的指标进行了测试,测试结果表明该PLL输出10 GHz时相位噪声优于-109 dBc/Hz@1 kHz,该指标与直接式频率合成器实现的指标相当.     

X波段低相噪频率综合器设计

介绍了一种X波段低相噪频率综合器的实现方法。采用混频环与模拟高次倍频相结合的技术,实现X波段跳频信号的产生。采用该技术实现的频率综合器杂散抑制可达-68 d Bc,相噪优于-99 d Bc/Hz@1 k Hz,-104 d Bc/Hz@10 k Hz,-106 d Bc/Hz@100 k Hz。重点论述了所采用的低相噪阶跃倍频的关键技术,详细分析了重要指标及其实现方法,实测结果证明采用该方法可实现给定指标下的X波段低相噪频率综合器。     

一种X波段低相噪跳频源的设计

基于小数分频锁相环HMC704LP4设计了一种X波段跳频源,具有相位噪声低、杂散低、体积小的特点。针对指标要求拟定设计方案,简述设计过程,给出设计参数,对关键指标进行分析仿真,并给出测试曲线。     

An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer

Although some papers have qualitatively analyzed the effect of charge pump mismatch on phase noise and spurs in sigma-delta fractional-N frequency synthesizer, few of them have addressed this topic quantitatively. An analytical model is proposed in this paper to describe the behavior of charge pump mismatch and the corresponding phase noise. Numerical simulation shows that this model is of high accuracy and can be applied to the analysis of in-band phase induced by the charge pump mismatch in sigma-delta fractional-N PLL frequency synthesizer. Most importantly, this model discloses that 6 dB reduction of in-band phase noise due to charge pump mismatch can be achieved by halving the charge pump mismatch ratio. After studying the typical topologies of sigma-delta modulators (SDM), we proposed some strategies on the selection of SDM in frequency synthesizer design. Our analytical model also indicates that eliminating the charge pump mismatch is one major path towards the in-band phase noise reduction of the sigma-delta frequency synthesizer. Xiaojian Mao was born in Jiangsu Province, China, in 1978. He received the B.S. degree in electronic engineering from Jilin University, Changchun, China, in 2000. He is currently pursuing the Ph.D. degree in circuits and systems at Department of Electronic Engineering of Tsinghua University, Beijing, China. His current research includes frequency synthesizers and phase-locking and clock recovery for high-speed data communications. And His PhD thesis title is “Design and Analysis of Sigma-Delta Fractional-N PLL Frequency Synthesizer.” Huazhong Yang received BS, MS, and PhD Degrees in electronics engineering from Tsinghua University, Beijing, in 1989, 1993, and 1998, respectively. He is a Professor and Head of the Circuits and Systems Division in the Department of Electronic Engineering at Tsinghua University, Beijing. His research interests include CMOS radio-frequency integrated circuits, VLSI system structure for digital communications and media processing, low-voltage and low-power circuits, and computer-aided design methodologies for system integration. He has authored and co-authored 6 books and more than 100 journals and conference papers. He was the winner of Chinas National Palmary Young Researcher Award in 2000. Hui Wang received the B.S. degree from Department of Radio Electronics, from Tsinghua University, Beijing, China. She was a visiting scholar at Stanford University, CA, USA from February 1991 to September 1992. Currently she is a Professor of the Circuits and Systems Division in the Department of Electronic Engineering and the deputy dean of academic affairs office at Tsinghua University, Beijing, China. Her research interests include modeling and simulation of radio-frequency CMOS integrated circuits, automatic design methodology for low voltage and low-power integrated circuits, and interconnect modeling and synthesis for deep submicron system-on-a-chip. She has authored and co-authored 4 books and over 70 papers. She was a primary research of TADS-C4 which gained a third-grade prize for the national progress in science and technology in China in 1993.     

An ultra-low power ISM-band integer-N frequency synthesizer dedicated to implantable medical microsystems

In this article, the architectural choices and design of a fully integrated integer-N frequency synthesizer operating in the 902–928 MHz Industrial, Scientific and Medical (ISM) band is presented. This frequency synthesizer, optimized for ultra-low power operation, is being integrated in the transceiver of an implantable wireless sensing microsystem (IWSM), which is dedicated to in vivo monitoring of biological parameters such as temperature, pressure, pH, oxygen, and nitric oxide concentrations. This phase-locked loop-based synthesizer includes a 1.830 GHz LC voltage-controlled oscillator (VCO) using a 10 nH on chip inductor. Varactors are implemented using P+ in N-well diodes for their linearity and high quality factor. The transistors of the VCO are operated in moderate inversion, and their bias point was chosen using the g _m/I _d design methodology. The output of the VCO, operating at twice the ISM frequency band, is divided by 2 to generate differential, quadrature versions of the carrier. Power minimization of the programmable divider was achieved by designing the latches and flip-flops using appropriate circuit techniques such as True Single Phase Clocking (TSPC) and first-type Dynamic Single Transistor Clocking (DSTC1) depending on their operating frequency. The power consumption of the proposed synthesizer is 580 μW under 1 V; almost an order of magnitude lower compared to that of recent synthesizer designs having a similar architecture.     

A dual-band frequency synthesizer for CMMB application with low phase noise

A wide-band frequency synthesizer with low phase noise is presented.The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range.This PLL is fabricated with 0.35μm SiGe BiCMOS technology.The measured result shows that the RMS phase error is less than 1°and the reference spur is less than -60 dBc.The proposed PLL consumes 20 mA cu...     

一种应用于CMMB的双频段低噪声频率合成器

A wide-band frequency synthesizer with low phase noise is presented. The frequency tuning range is from 474 to 858 MHz which is compatible with U-band CMMB application while the S-band frequency is also included. Three VCOs with selectable sub-band are integrated on chip to cover the target frequency range. This PLL is fabricated with 0.35 μ m SiGe BiCMOS technology. The measured result shows that the RMS phase error is less than 1^o and the reference spur is less than –60 dBc. The proposed PLL consumes 20 mA current from a 2.8 V supply. The silicon area occupied without PADs is 1.17 mm².     

超宽带低相噪频率合成器的实现

介绍了1种频率范围4~16GHz,步进1MHz的超宽带、小步进、低相噪频率合成器的实现方法。通过混频式锁相环方案,大大降低了环内分频比,选用低相噪器件,以及采用了梳状谱发生器代替传统的大步进环等措施,使输出实现了低相噪指标。在16GHz输出时,相位噪声指标小于-90dBc/Hz(@10kHz)。并通过对合成器指标的分析,阐述了在混频环设计过程中需要注意的一些问题。     

X波段低相噪宽频带雷达频率综合器设计

随着雷达导引头在弹载方面的广泛应用,导引头的抗电子干扰能力成为一项关键技术。雷达频率综合器作为雷达系统的核心部件,其产生本振信号的质量对雷达系统的抗电子干扰能力具有决定性影响,这对本振信号的跳频带宽、相位噪声、杂波抑制度、平坦度等参数指标提出了更高的要求。本文运用直接数字频率合成(DDS)技术和先进设计系统(ADS)仿真技术进行宽带阻抗匹配,采取有效信号串扰隔离技术,使雷达频率综合器的X波段本振信号的各项指标得到明显改善。通过实验测试,本振信号可以实现快速跳频,跳频带宽达到500 MHz,提高了雷达的抗干扰能力;相位噪声优于-98 dBc/Hz@1 kHz,有效改善了雷达导引头的接收灵敏度。