Long-term bias temperature reliability of P+ polysilicongated FET devices

An instability was found to be associated with +BT stress for P ⁺ poly-gated NMOSFETs (PNMOS) and PMOSFETs (PPMOS), but not with the N⁺ poly-gated devices (NNMOS and NPMOS). The instability with the P⁺ poly-gated devices, which is a decrease in threshold voltage (V_t) and an increase in interface state density (D_it), was significantly reduced following N₂ annealing at 400°C. It is shown that adequate reliability for P⁺ poly-gated devices can be achieved for VLSI technologies     

An analytical threshold voltage model of NMOSFETs with hot-carrier induced interface charge effect

An analytical threshold voltage model of NMOSFETs including the effect of hot-carrier-induced interface charges is presented. A step function describing the interface charge distribution along the channel is used to account for the hot carrier induced damage, and a pseudo-2D method is applied to derive the surface potential. The threshold voltage model is then developed by solving the gate-to-source voltage at the onset of surface inversion where the minimum surface potential equals the channel potential. Both the drain-induced barrier lowering (DIBL) and body effects are included in the present model as well. The present threshold voltage model is validated for both fresh and damaged devices. The results show that the threshold voltage shifts upward and approaches a maximum value with negative interface charges and shifts downward and reaches a minimum value with positive interface charges as the interface charge region length is increased from zero to the channel length. Model is successfully verified using simulation data obtained from TCAD (technology-based computer-aided design).     

SOI器件的增强短沟道效应模型

为了探索SOI器件总剂量辐照后阈值电压漂移量和沟道长度的关系,利用器件模拟软件ISE TCAD,对不同沟道长度的PDSOI NMOS管进行了总剂量辐照模拟.模拟结果表明,随着沟道长度的减小,背沟道MOS管阈值电压漂移越来越大,并且漂移量和辐照偏置密切相关,称此效应为SOI器件的增强短沟道效应.以短沟道效应理论为基础对此效应的机理进行了解释,并以短沟道效应模型为基础对此效应提出了一个简洁的阈值电压漂移模型,通过对ISE模拟结果进行曲线拟合对所提出的模型进行了验证.     

A temperature-stabilized SOI voltage reference based on thresholdvoltage difference between enhancement and depletion NMOSFET's

A temperature-stabilized silicon-on-insulator (SOI) voltage reference is presented. It is based on the threshold voltage difference between enhancement and depletion SOI NMOSFETs that have the same channel doping concentration but of opposite type. The circuit has been realized on a SIMOX wafer using an n⁺-poly gate and a LOCOS isolation process. The threshold voltages of the enhancement and depletion SOI NMOSFETs show almost the same temperature dependence when a suitable back-gate bias is applied. Experimental results show a temperature coefficient of 33.8 p.p.m./°C over the temperature range of -50 to 75°C. The variation of threshold voltage difference with temperature is small, and this circuit becomes more advantageous as the front-gate oxide is scaled down or the bias current is reduced     

SOI MOSFET自加热效应测试方法

为研究自加热效应对绝缘体上硅(SOI)MOSFET漏电流的影响,开发了一种可同时探测20 ns时瞬态漏源电流-漏源电压(Ids-Vds)特性和80μs时直流静态Ids-Vds特性的超快脉冲I-V测试方法。将被测器件栅漏短接、源体短接后串联接入超快脉冲测试系统,根据示波器在源端采集的电压脉冲的幅值计算漏电流受自加热影响的动态变化过程。选取体硅NMOSFET和SOI NMOSFET进行验证测试,并对被测器件的温度分布进行仿真,证实该方法用于自加热效应的测试是准确有效的,能为建立准确的器件模型提供数据支撑。采用该方法对2μm SOI工艺不同宽长比的NMOSFET进行测试,结果表明栅宽相同的器件,栅长越短,自加热现象越明显。     

Hot-carrier reliability of submicron NMOSFETs and integrated NMOS low noise amplifiers

The effects of hot-carrier stress (HCS) on the performance of NMOSFETs and a fully integrated low noise amplifier (LNA) made of NMOSFETs in a 0.18 μm CMOS technology are studied. The main effects of HCS on single NMOSFETs are an increase in threshold voltage and a decrease in channel carrier mobility, which lead to a drop in the biasing current of the transistors. In the small-signal model of the transistor, hot-carrier effects appear as a decrease in the transconductance and an increase of the output conductance. No clear change was observed in the parasitic gate–source and gate–drain capacitances in the devices under test due to hot carriers. The main effects of hot carriers in the LNA were a drop of the power gain and an increase of its noise figure. The input and output matching, S₁₁ and S₂₂, slightly increased after hot-carrier stress. The third- order input-referred intercept point (IIP3) of the LNA improved after stress. This is believed to be due to the improvement of the linearity of the current–voltage (I–V) characteristics of the transistors in the LNA at the particular operating point where they were biased.     

Gate length dependence of the shallow trench isolation leakage current in an irradiated deep submicron NMOSFET

The effects of gamma irradiation on the shallow trench isolation(STI)leakage currents in a 0.18μm technology are investigated.NMOSFETs with different gate lengths are irradiated at several dose levels.The threshold voltage shift is negligible in all of the devices due to the very thin oxide thickness.However,an increase in the off-state leakage current is observed for all of the devices.We believe that the leakage is induced by the drain-to-source leakage path along the STI sidewall,which is formed by the positive trapped charge in the STI oxide.Also, we found that the leakage is dependent on the device’s gate length.The three-transistor model(one main transistor with two parasitic transistors)can provide us with a brief understanding of the dependence on gate length.     

An accurate two-dimensional CAD-oriented model of retrograde doped MOSFETs for improved short channel performance

An analytical CAD-oriented model for short channel threshold voltage of retrograde doped MOSFETs is developed. The model is extended to evaluate the drain induced barrier lowering parameter (R) and gradient of threshold voltage. The dependence of short channel threshold voltage and R on thickness of lightly doped layer (d) has also been analyzed in detail. It is shown that a retrograde doping profile reduces short channel effects to a considerable extent. A technique is developed to optimize the device parameters for minimizing short channel effects. The results so obtained are in close proximity with published data.     

Elimination of surface state induced edge transistors in high voltage NMOSFETs for flash memory devices

The abnormal leakage failure in high voltage NMOSFETs is investigated by measuring the subthreshold hump characteristics. Gated diode, width and substrate bias dependence of the I_D-V_GS characteristics, and two-terminal I-V measurements between the source and the drain reveal that the hump characteristic is caused by the surface states, not by the gate field crowding at STI edges. The numerical calculation shows that the high voltage NMOSFETs are very delicate to leakage failure by a small amount of surface state (10¹¹ /cm²), due to the thick gate oxide and very low doping concentration for high voltage operation (>25 V). A thermal oxidation with the thickness of 1.0 nm successfully eliminates the parasitic corner transistors without changing electrical characteristics of the targeted transistors in current state of the art flash memory devices.     

Enhancement-Mode GaAs n-Channel MOSFET

This letter introduces the first enhancement-mode GaAs n-channel MOSFETs with a high channel mobility and an unpinned Fermi level at the oxide/GaAs interface. The NMOSFETs feature an In_0.3Ga_0.7 As channel layer, a channel mobility of up to 6207 cm²/Vmiddots, and a dielectric stack thickness of 13.1-18.7 nm. Enhancement-mode NMOSFETs with a gate length of 1 mum, a source/drain spacing of 3 mum, and a threshold voltage of 0.05 V show a saturation current, transconductance, on-resistance, and subthreshold swing of 243 mA/mm, 81 mS/mm, 8.0 Omegamiddotmm, and 162 mV/dec, respectively     

应变SiGe沟道PMOSFET阈值电压模型

首先建立了应变SiGe沟道PMOSFET的一维阈值电压模型,在此基础上,通过考虑沟道横向电场的影响,将其扩展到适用于短沟道的准二维阈值电压模型,与二维数值模拟结果呈现出好的符合。利用此模型,模拟分析了各结构参数对器件阈值电压的影响,并简要讨论了无Sicap层器件的阈值电压。     

A simple analytical model for the electrical characteristics of depletion-mode MOSFET's with application to low-temperature operation

A simple analytical model for depletion-mode MOSFET's is developed based on the gradual channel approximation and taking into account carrier freeze-out onto impurity sites implanted for threshold voltage modification. Theory is found to be in reasonable agreement with experimental results for n-channel depletion-mode MOSFET's at room temperature and at 77 K. It is shown that the common methods used for enhancement-mode devices to determine carrier channel mobility and threshold voltage, respectively, from the slope and voltage intercept of the current-gate voltage characteristics are invalid for depletion-mode devices. By comparison of enhancement and depletion devices on the same chip, it is shown that the processes associated with ion implantation had no effect on electron channel mobility at room temperature and caused at most a 25-percent reduction at 77 K. The model also is applicable to buried p-channel devices as used in CMOS technologies.     

Temperature dependence of threshold voltage in thin-film SOIMOSFETs

A first-order model for the temperature dependence of threshold voltage in thin-film silicon-on-insulator (SOI) n-MOSFETs is described. The temperature dependence of the threshold voltage of thin-film SOI n-channel MOSFETs is analyzed. Threshold voltage variation with temperature is significantly smaller in thin-film (fully depleted) devices than in thick-film SOI and bulk devices. The threshold voltage is shown to be dependent on the depletion level of the device, i.e. whether it is fully depleted or not. There exists a critical temperature below which the device is fully depleted, and above which the device operates in the thick-film regime     

Measurement and modeling of a new width dependence of nmosfet degradation

NMOS transistors with widths between 1.2μm and 10μm and length of 0.8μm have been stressed for up to 5000 hours. Investigating the threshold voltage shift a new width dependence of degradation has been measured, analysed and modeled by a simple theory. Because of the increasing degradation of NMOSFETs with decreasing width this effect will be more and more important for small-channel LOCOS transistors.     

Comparative study of leakage power in CNTFET over MOSFET device

A comparison of the CNTFET device with the MOSFET device in the nanometer regime is reported.The characteristics of both devices are observed as varying the oxide thickness.Thereafter,we have analyzed the effect of the chiral vector and the temperature on the threshold voltage of the CNTFET device.After simulation on the HSPICE tool,we observed that the high threshold voltage can be achieved at a low chiral vector pair.It is also observed that the effect of temperature on the threshold voltage of the CNTFET is negligibly small.After that,we have analyzed the channel length variation and their impact on the threshold voltage of the CNTFET as well as MOSFET devices.We found an anomalous effect from our simulation result that the threshold voltage increases with decreasing the channel length in CNTFET devices; this is contrary to the well known short channel effect.It is observed that at below the 10 nm channel length,the threshold voltage is increased rapidly in the case of the CNTFET device,whereas in the case of the MOSFET device,the threshold voltage decreases drastically.     

Analysis of different parameters of channel material and temperature on threshold voltage of CNTFET

Carbon nanotubes have some unique features and special properties that offer a great potential for nano-electronic devices. In this paper, we have analyzed the effect of chiral vector, metal work function, channel length and High-K dielectric on threshold voltage of CNTFET devices. We have also compared the effect of oxide thickness on gate capacitance and justified the advantage of CNTFET over MOSFET in nanometer regime. Simulation on HSPICE tool shows that high threshold voltage can be achieved at low chiral vector in CNTFET. It is also observed that the temperature has a negligible effect on threshold voltage of CNTFET. After that we have simulated and observed the effect of channel length variation on threshold voltage of CNTFET as well as of MOSFET devices and given a theoretical analysis on it. We found an unusual, yet, favorable characteristics that the threshold voltage increases with decreasing channel length in CNTFET devices in deep nanometer regime especially when the gate length is around 10 nm; which is quite contrary to the well known short channel effects in MOSFET. It is observed that at or below 10 nm channel length the threshold voltage increases rapidly in case of CNTFET device whereas in case of MOSFET device the threshold voltage decreases drastically.     

Threshold voltage controllability in double-diffused-MOS transistors

The sensitivity of double-diffused metal-oxide-semiconductor (D-MOS) transistor threshold voltage to fabrication process variations has been studied. Computed impurity profiles are used to study the process dependencies. For the double diffused process, the channel predeposition is shown to be the most critical step in threshold voltage control for long channel devices. Experimental results confirm this relationship. Process considerations appropriate for the fabrication of short channel D-MOS devices are also presented. Computed variations of threshold voltage with expected process tolerances for the channel predeposition are consistent with experimental results. Computer results show that for D-MOS deviceswith source junction depths of about 1 µm and channel lengths greater than 2 µm, threshold voltage can be controlled to ±20 percent using thermal diffusion and ±5 percent using ion implanted predeposition. Greater variation in threshold voltage is found for shorter channel lengths.     

Quantization effects in inversion layers of PMOSFETs on Si (100)substrates

The 2-D hole gas distributions within inversion layers of PMOSFETs have been evaluated by solving the coupled Schrodinger equation and Poisson equation self-consistently based on the effective mass approximation with the light hole and heavy hole subbands taken into account. The threshold voltage shift resulting from the carrier redistribution due to quantization effects is found to be more significant for PMOSFETs than NMOSFETs on (110) Si substrates. For a certain substrate doping concentration the threshold voltage shift from the classical value due to quantization effects is found to be a combination of substrate band bending and oxide potential differences between the classical and the quantum mechanical models     

Channel length influenced contribution of hole and electron trapping effect to threshold voltage stability in organic field effect transistors

Effect of channel length on hysteresis and threshold voltage shift in copper phthalocyanine (CuPc) based organic field effect transistors was studied. Contrary to expectation, longer channel length devices exhibited minimum threshold voltage shift. Influence of channel length on the contribution of hole and electron trapping to threshold voltage stability was determined. Shortest channel length devices exhibited highest electron trapping effect while longest channel devices exhibited minimum hole as well as electron trapping. Lower hole trap effect for longer channel length devices was suggested to be due to reduced longitudinal field between source and drain electrodes while minimum electron trapping was attributed to suppression of drain current by increased hole trap centres.     

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

High leakage current in deep-submicrometer regimes is becoming a significant contributor to power dissipation of CMOS circuits as threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for estimation and reduction of leakage power, especially for low-power applications. This paper reviews various transistor intrinsic leakage mechanisms, including weak inversion, drain-induced barrier lowering, gate-induced drain leakage, and gate oxide tunneling. Channel engineering techniques including retrograde well and halo doping are explained as means to manage short-channel effects for continuous scaling of CMOS devices. Finally, the paper explores different circuit techniques to reduce the leakage power consumption.