An integrated approach for hierarchical verification of VLSI mask artwork

An integrated design system (IDS) for handcrafted digital VLSI circuits is presented. Developed over a two-year period, IDS consists of both in-house and third-party software, integrated with a hierarchical top-down design methodology. A key component of IDS is the Structured LAyout VErification (SLAVE) program for electrical verification of mask artwork. Implementation of a top-down design methodology allows SLAVE to use the separate hierarchical representations in the logic, circuit, and layout models to completely verify the connectivity of the mask layout. SLAVE has been successfully adapted to both bipolar and CMOS technologies; it provides error detection down to specific signal nets and device nodes and is extremely fast. SLAVE typically runs under 70 min on a VAX 11/780 for a complex IC containing up to 50K discrete devices and is modeled using six levels of hierarchical nesting.     

Reliability evaluation of tungsten donut-via as an element of the highly robust metallization

The typical via layout in CMOS technology with AlCu-metallizations and tungsten via is cylindrical. Common vias have a size as small as possible in the related process. More challenging application, temperature and mission profiles require higher robustness of a metallization [1,2]. Via arrays of small common vias are in use to the transfer of higher currents [3]. But the typical via array layout is not the best layout for applications which are faced to high mechanical stress because via arrays metal layer connections make these parts in the stack inflexible.The developed so called highly robust metallization is optimized for applications with extended operating conditions regarding higher currents and temperatures as well as mechanical stress [4]. Donut-Vias are elements of the highly robust metallization for the interconnection of highly robust metal lines. The paper shows the layout of a Donut-Via and explains the benefits and limits of the new layout by simulation and test results.     

The influence of TiN ARC thickness on stress-induced void formationin tungsten-plug vias

This paper describes a new failure mechanism in W-plug vias, and the process conditions which enhance it. For submicron technologies, the limiting factor in interconnect reliability performance is increasingly dominated by the electromigration resistance of tungsten-plug vias. We have observed that under certain experimental conditions, early electromigration failures can be induced in via-chain test structures. We have demonstrated that these are caused by stress-induced void formation in the metal line immediately beneath the tungsten plug. This is thought to be due to highly localized film stress around the base of the plug, which can be minimized by increasing the thickness of the TiN anti-reflective coating (ARC). This has the effect of reducing the incidence of early failure by suppressing the stress-induced failures     

Electromigration failure distributions of dual damascene Cu /low – k interconnects

The reliability of dual damascene Cu/low – k interconnects is limited by electromigration – induced void formation at vias. In this paper we investigate via void morphologies and associated failure distributions at the low percentiles typical of industry reliability requirements. We show that Cu/low – k reliability is fundamentally limited by the formation of slit – voids under vias. Using experimental and simulation approaches we clarify the practical importance of apparent incubation phenomena associated with this failure mode.     

A modeling methodology for thermal analysis of the PCB structure

A modeling methodology is proposed for the thermal analysis of the PCB structure based on integrating both the FVM-based numerical solution and the Fourier-series-based analytical solution of temperature. The heat spreading through tracks and the vertical heat transfer through vias are taken into account in a numerical way and regarded as the additional thermal boundary conditions of insulating layers, which are assumed to be homogeneous from an analytical point of view. A methodology based on the vertex-centered Cartesian-grid Finite Volume Method is also proposed for the electric analysis of PCB tracks in order to take into account the temperature-dependent Joule heating effect, thus the current carrying capacity of tracks can be estimated as well. The necessary and sufficient condition for solving electric distributions in multi-terminal tracks is discussed, described and verified through both the analysis of the equivalent resistor network in a multi-terminal track and the mathematical analysis of a matrix equation, which correlates terminal currents with terminal electric potentials. In addition, the method for analyzing the multilayer structure is also discussed. A thermal solver was developed in MATLAB based on the methodology. Several layouts were modeled in the solver and COMSOL to test the validity of the methodology and to investigate the influence factors of the solution. Based on the analysis and comparisons, mesh density and the number of eigenvalues are the main influence factors. The vertical and horizontal heat transfer contributions of vias were also investigated by modeling the footprint layout of a power mosfet in order to test the modeling assumptions. Finally, the consistency between the modeling results and the reference results was found. Both the advantages and disadvantages of the methodology are discussed throughout the analysis.     

Early-life reliability prediction methodology for integrated circuits

A methodology for predicting early failures due to random process flaws in integrated circuits is proposed. Early failures are not intrinsic failures, and therefore the current practice of extrapolating intrinsic life-test distributions to estimate early-life reliability is incorrect and yields optimistic results. Early failure mechanisms are classified into three categories based on the physical understanding and statistical data available for the mechanism. Subpopulations with defect-related failure distributions are characterized by a knowledge of the effects of defects in category one and using past field return data in category two. The third category, associated with failures due to applied overstress or misuse, iis characterized by field return, technology and design data. Modeling early failures at the ‘micro’ level (subsystem level) is an improvement over the existing practice of characterizing infant mortality based on field returns at the ‘macro’ level (chip level). Using the proposed methodology, process and design improvements can be incorporated in the early failure predictions. Examples showing the application of this methodology are included.     

A test structure for contact and via failure analysis in deep-submicrometer CMOS technologies

Reliability and yield of CMOS integrated circuits are becoming more and more dependent on interconnect elements (contacts, vias, and metal lines). These are therefore considered to represent one of the main limits to the future scaling down of integration processes. Indeed, the continuous growth of semiconductor technology integration density has led to billions of transistorson a single chip and, hence, the evaluation of process yield asks for failure rate sensitivity in the order of 1 fault per billion. This paper presents a test structure which allows evaluating the contribution of interconnects to reliability and manufacturing yield degradation in high-density CMOS technologies. The test structure is based on a suitable array of contacts and vias, and has been conceived to measure the statistical distribution of interconnect failures. The main advantages of the proposed test structure are: the reduced number of test pads required measuring an extremely high amount of contacts and vias; the high sensitivity, which allows also resistive contacts or vias to be identified; and the possibility to determine the physical location of interconnect faults, thus simplifying the subsequent physical failure analysis. The test structure was integrated in 130 nm CMOS technology. Experimental results demonstrate the effectiveness of the proposed solution.     

一种用于三层布线的分层算法

随着VLSI/LSI技术的发展,多层布线已能够实现。互连网络的分层问题就是要使得互连网络所需的通孔数最少。在通孔最小化问题中,如果布图拓扑逻辑已给出,这类问题被称为受限的通孔最小化(CVM)问题。本文针对三层布线中的CVM问题提出了一种分层算法,使得布图所需的通孔数最小化。应用此算法能获得比文献中所述更少的通孔数。     

Failure of electrical vias manufactured in thick-film technology when loaded with short high current pulses

The high-current failure of electrical interconnects (through-metalized vias) manufactured in thick-film technology is investigated. A large number of vias were measured in a four-wire-setup by applying short time high-current pulses. The experimental conditions ensured that approximately half of the tested vias were destroyed during the tests. The high-current failure mechanism was identified to be a kind of a self-accelerating melting process. It was also implemented in a “Finite Element Method” (FEM)-model. The FEM-model delivered not only the time-dependent voltage drops over the through holes (which is proportional to the through hole resistance), but also the time-dependent temperature, conductivity, and current density distributions inside of the vias during current load. Input parameters for the model were material properties and sample geometries. Analyzed cross-section micrographs of destroyed vias and the temperature maxima received from the FEM-model agreed well. Furthermore, measured and modeled voltage drops during failure were compared and agreed also very well.     

结合场景描述的文本生成图像方法

研究基于场景描述文本生成对应图像的方法,针对生成图像常常出现的对象重叠和缺失问题,提出了一种结合场景描述的生成对抗网络模型。首先,利用掩模生成网络对数据集进行预处理,为数据集中的对象提供分割掩模向量。然后,将生成的对象分割掩模向量作为约束,通过描述文本训练布局预测网络,得到各个对象在场景布局中的具体位置和大小,并将结果送入到级联细化网络模型,完成图像的生成。最后,将场景布局与图像共同引入到布局鉴别器中,弥合场景布局与图像之间的差距,得到更加真实的场景布局。实验结果表明,所提模型能够生成与文本描述更匹配的图像,图像更加自然,同时有效地提高了生成图像的真实性和多样性。     

Investigation of the short-time high-current behavior of vias manufactured in hybrid thick-film technology

In this contribution, the short-time high-current behavior of electrical interconnects (through-metalized vias) manufactured in thick-film technology is investigated. Such vias are reliable devices for small currents, but their behavior when high currents are applied for short times has not been fully understood. Therefore, in a four-wire-setup, short-time high-current pulses were applied to single vias and the resulting transient voltage drops were measured. Furthermore, an FEM-model was developed to simulate this voltage drops as well as the time-dependent temperature distributions inside of the vias. Input parameters were material properties and sample geometries. The good agreement between the measured and the simulated time-dependent voltage drops validated the model. The resulting temperature distributions are an appropriate engineering tool for the further development of vias with respect to reliability and high ampacity.     

Circuit reliability simulator for interconnect, via, and contactelectromigration

A model for predicting Al interconnect and intermetallic contact/via electromigration time-to-failure under arbitrary current waveform is incorporated in a circuit electromigration reliability simulator. The simulator can (1) generate layout advisory for width and length of each interconnect, and the number of contacts and vias at each node in a circuit, and (2) estimate the overall circuit electromigration failure rate and/or cumulative percent failure as functions of time, temperature, voltage, frequency, and previous stress (e.g., burn-in)     

MCM-C基板上的多层互连及厚膜电阻的可靠性研究

重点研究了MCM-C基板中多层互连和厚膜电阻的可靠性.试验采用温度应力和电应力的双应力加速寿命试验.试验发现,温度小于180℃时互连失效在MCM-C基板失效中占主要地位,膜电阻失效相对互连失效可忽略不计.在温度高于180℃时膜电阻失效将起较大作用,即膜电阻比互连温度加速系数要大.重点计算了膜电阻和互连寿命分布及加速系数.     

Reliability improvement by the suppression of keyhole generation in W-plug vias

This paper describes a mechanism of failures in W-plug vias due to the keyhole generation, and presents the process conditions which enhance the reliability of W-plug vias. For a high aspect ratio via-hole, one of the limiting factors in the reliability of the W-plug is the generation of the keyholes. We have investigated the sensitivities of corresponding technologies and conditions to the generation of the keyholes during the plug process. They include deposition technologies of TiN and deposition conditions of W. Based on the SEM observation and the electromigration failure test, the process conditions of TiN and W have been optimized.     

Global (interconnect) warming

This article presents a comprehensive analysis of the thermal effects in advanced high-performance VLSI interconnect systems arising due to self-heating under various circuit conditions, including electrostatic discharge (ESD). Technology (Cu, low-k, etc.) and scaling effects on the thermal characteristics of the interconnects, and on their electromigration (EM) reliability, have been analyzed simultaneously, which have important implications for providing robust and aggressive deep sub-micron (DSM) interconnect design guidelines. The analysis takes into account the effects of increasing interconnect (Cu) resistivity with decreasing line dimensions and the effect of a finite barrier metal thickness. Furthermore, the impact of these thermal effects on the design (driver sizing) and optimization of the interconnect length between repeaters at the global-tier signal lines are investigated. Finally, the reliability implications for minimum-sized vias in optimally buffered signal nets will also be quantified     

Quantifying the effect of local interconnects on on-chip power distribution

Existing methods to analyze and optimize on-chip power distribution networks typically focus only on global power network modeled as a two-dimensional mesh. In practice, current is supplied to switching transistors through a local power network at the lower metal layers. The local power network is connected to a global network through a stack of vias. The effect of these vias and the resistance of the local power network are typically ignored when optimizing a power network and placing decoupling capacitors. By modeling the power distribution network as a three-dimensional mesh, the error due to ignoring via and local interconnect resistances is quantified. It is demonstrated that ignoring the local power network and vias can both underestimate (by up to 45%) or overestimate (by up to 50%) the effective resistance of a power distribution network. The error depends upon multiple parameters such as the width of local and global power lines and via resistance. A design space is also generated to indicate the valid width of local and global power lines where the target resistance is satisfied. It is shown that a wider global network can be used to obtain a narrower local network, providing additional flexibility in the physical design process since routability is an important concern at lower metal layers. At high via resistances, however, this approach causes significant increase in the width of a global power network, indicating the growing significance of local power network and vias.     

Critical area extraction for soft fault estimation

Algorithms are presented for extracting the critical area associated with extra and missing material soft faults of an integrated circuit from the mask layout. These algorithms have been implemented within the Edinburgh Yield Estimator (EYE) tool which permits efficient extraction of the critical area from an arbitrary mask layout. Accurate estimates of device critical area of even the largest devices can be obtained in a reasonable time using the sampling version of the tool. The application of these algorithms to defect related reliability is explored and results reported that compare the susceptibility to soft faults before and after layout modifications intended to enhance manufacturing yield. These results suggest that yield enhancement techniques can have a significant impact on defect-related device reliability     

A simulation study of copper reflow characteristics in vias

The reliable and complete filling of vias and trenches with an appropriate metal is an important process in the fabrication of microelectronic components. Due to its favorable electronic properties and its reliability, copper is a common choice for replacing aluminum as a metallization material. One metallization procedure of interest is the sputter reflow of copper. The sputter reflow process begins with depositing copper via traditional sputter technologies. The films are subsequently made to fill micrometer and submicrometer trenches and vias through surface diffusion enhanced by annealing. This paper studies fundamental considerations such as deposition rates, underlayer material, and transport mechanisms through numerical simulation using the process simulators SIMSPUD and GROFILMS. The simulations are further used to study via filling using Cu reflow and alternative methods including in situ annealing, three-step deposition, and a four-stage deposition-chemical mechanical polishing procedure. Simulation results are presented as depictions of the film on the feature scale. A discussion of the algorithmic solutions to the three-dimensional problems associated with vias is also provided     

A new failure mechanism by corrosion of tungsten in a tungsten plug process

The tungsten filled via plug process is commonly used in sub-half micron CMOS process technologies. As process technologies shrink beyond the 0.25 μm generation, the metal overlap over the via also reduces. This results in vias not fully covered by the overlying interconnect lines. In the evaluation of such structures, we have observed a new failure mechanism resulting in completely unfilled vias due to electrochemical corrosion accelerated by a positive charge on specific structures. This positive charge is collected by the metal connected to the via during metal plasma etch processing and results in electro-chemical corrosion during a subsequent solvent strip process. The charge collection is found to be dependent on the geometry of the test structure. The corrosion rate is dependent on the amount of charge and the solvent pH. Methods to limit this corrosion are discussed.     

利用热红外偏振成像技术识别伪装目标

介绍了热红外偏振测量的原理,采用利用偏振信息在红外图像中识别伪装遮障的方法研制了一台热红外偏振成像仪,编写了偏振信息分析软件。利用该系统对地物背景（土壤）中的不同种类金属目标板及红外伪装遮障进行了热红外偏振成像探测实验。结果表明：在利用热红外偏振探测系统获得的Stokes矢量图中, 地物背景、金属目标板及红外伪装遮障的热红外偏振特性各不相同,并且和其红外辐射强度无关,相对红外强度探测更容易从地物背景中识别出金属目标板及红外伪装遮障。