The Effects of Si Submounts Containing Cu Thermal Vias on the Heat-Dissipation Characteristics of a High-Power Light-Emitting Diode Package

We investigated the effects of Si submounts containing Cu thermal vias on the heat-dissipation characteristics of a high-power light-emitting diode (LED) package. Simulations were used to determine the optimum conditions for effective heat dissipation from the LED. The optimum thickness of the Si submount containing the Cu thermal vias was 250 μm. The optimum heat flux area ratio between the Si submount and the LED chip was 25. The thermal resistance of an Si submount 250 μm thick and 25 mm² in area was 1.85 K/W without Cu vias. This value decreased to 1.50 K/W on incorporation of the 400-μm-diameter Cu vias. In addition, the total thermal resistance of the LED package structure was improved from 9.7 K/W to 8.3 K/W on incorporation of the 400-μm-diameter Cu vias into the Si submount.     

DDFSGEN

This paper presents a functional compiler for the automatic design of Direct Digital Frequency Synthesizer (DDFS) integrated circuits (ICs) using a ROM based table look-up architecture. The compiler allows the user to specify high-level specifications such as the acceptable spurious response and it generates the IC architecture, floorplan, and layout. To construct the layout for different specifications, a library of parameterized macrocells has been developed in 1.2 μm CMOS technology. A test chip with a quadrature DDFS module has been generated, using the compiler, and fabricated. The chip has two input signals: one is for frequency control while the other is for phase initialization. Input and output word lengths are 16 bits and 6 bits respectively. The chip complexity is approximately 12,000 transistors (DDFS core) and the die size is 4.8×2.9mm ². A maximum sample rate of 80 MHz has been attained implying a maximum sine (cosine) output frequency of 40 MHz and a frequency resolution of 1.22 kHz. The maximum spurious level measured is ?46 dB.     

基于PDP扫描驱动芯片的LQFP封装热特性研究

研究了LQFP封装的96路等离子平板显示(PDP)扫描驱动芯片的封装热特性,利用有限元法对所建立的封装模型进行数值求解,并与实测结果进行比较,验证了模型求解的可靠性与准确性。研究表明,在集成电路封装设计中,增大散热基板面积、优化引线框架、提高封装热导率,对于散热性能的提高非常有效,而在外围设计中,增大印制电路板(PCB)有效覆铜面积、增加PCB有效过孔数、在芯片顶部添加散热片、加大空气流速都可使芯片散热能力显著增强。     

Modeling Thermal Stresses in 3-D IC Interwafer Interconnects

We present a finite-element-based analysis to determine if there are potential reliability concerns due to thermally induced stresses in interwafer copper via structures in three-dimensional (3-D) ICs when benzocyclobutene (BCB) is used as the dielectric adhesive to bond wafers. We first partially validate our approach by comparing computed results against two types of experimental data from planar ICs: 1) volume-averaged thermal stresses measured by X-ray diffraction in an array of parallel Cu lines passivated with TEOS and 2) studies of failures induced by thermal cycling via chain structures embedded in SiLK or SiCOH. In the volume-averaged thermal stress study, predicted stress slopes (dsigma/dT) agree well with other modeling results. Our computed stress slopes agree reasonably well with experimental data along the Cu line direction and normal to the Cu lines surface, but we underestimate the stress slope across the Cu line. In the case of via chains, computed von Mises stresses agree with the results of thermal cycle experiments; we predict failure when SiLK is used as a dielectric and predict no failure when SiCOH is used as the dielectric. The approach is then employed to study thermal stresses in interwafer Cu vias in 3-D IC structures bonded with BCB. Simulations show that the von Mises stresses in interwafer Cu vias decrease with decreasing pitch at constant via size, increase with decreasing via size at constant pitch, and decrease with decreasing BCB thickness. We conclude that there is a concern regarding the stability of interwafer Cu vias. Guidelines for design parameter values are estimated, e.g., interwafer via size, pitch, and BCB thickness. For 2.6-mum-thick BCB, computations indicate that via size should be larger than 3 mum at a pitch of 10 mum to avoid plastic yield of Cu vias     

Study of Intermetallic Growth and Kinetics in Fine-Pitch Lead-Free Solder Bumps for Next-Generation Flip-Chip Assemblies

With continued advances in microelectronics, it is anticipated that next-generation microelectronic assemblies will require a reduction of the flip-chip solder bump pitch to 100 μm or less from the current industrial practice of 130 μm to 150 μm. With this reduction in pitch size, and thus in bump height and diameter, the interaction between die pad metallurgy and substrate pad metallurgy becomes more critical due to the shorter diffusion path and greater stress. Existing literature has not addressed such metallurgical interaction in actual fine-pitch flip-chip assemblies. This work studies intermetallic growth and kinetics in fine-pitch lead-free solder bumps through thermal aging of flip-chip assemblies. Based on this study, it is seen that Ni from the die pad diffuses to the substrate pad region and Cu from the substrate pad diffuses to the die pad region, thus the resulting intermetallic compounds at the die and substrate pad regions are influenced by the other pad as well. Such cross-pad interaction is much stronger in fine-pitch solder bumps with smaller standoff height. It is seen that the die pad region contains Ni₃P and (Cu,Ni)₆Sn₅ after thermal aging, while the substrate pad region contains Cu₃Sn and (Cu,Ni)₆Sn₅. By digitally measuring the thickness of the interfacial phases, the kinetics parameters and the activation energy were calculated for the growth of (Cu,Ni)₆Sn₅ on the substrate side. The Cu diffusion coefficient through the intermetallic compound (IMC) layer was found to be 0.03370 μm²/h, 0.1423 μm²/h, and 0.4463 μm²/h at 100°C, 125°C, and 150°C, respectively, and the apparent activation energy for the growth of compound layers was 67.89 kJ/mol.     

Modeling of Thermally Induced Stresses in Three-Dimensional Bonded Integrated Circuit Wafers

A finite-element model has been developed to investigate the potential reliability issues of thermally induced stresses in interwafer Cu via structures in three-dimensional (3D) integrated circuit (IC) wafers. The model is first partially validated by comparing computed results against experimental data on via test structures from planar ICs. Computed von Mises stresses show that the predicted failure agrees with the results of thermal cycle experiments. The model is then employed to study thermal stresses in interwafer Cu vias in 3D bonded IC structures. The results illustrate that there is a concern regarding the stability of interwafer Cu vias. Simulations show that the von Mises stresses in interwafer Cu vias decrease with decreasing pitch length at constant via size, increase with decreasing via size at constant pitch, and decrease with decreasing bonding thickness.     

A 5 Gb/s multi-mode transmitter with de-emphasis for PCI Express 2.0/USB 3.0

A versatile transmitter compatible SERDES system was fabricated in 55 nm CMOS technology. The proposed transmitter comprises a low-power and low-area driver with de-emphasis and a 10:1 serializer, meanwhile it supports power management to reduce the unnecessary dissipation and to complete the mode transition among four power modes. Furthermore, the transmitter is compatible with PCI Express 2.0/1.0 and also meets the USB 3.0 standard. The experimental results show this test chip passes PCI Express 2.0/1.0 TX compliance test and USB 3.0 TX compliance test. The chip occupies 0.033 mm² and consumes 33 mA at 5 Gb/s.     

Carbon Nanomaterials for Next-Generation Interconnects and Passives: Physics, Status, and Prospects

This paper reviews the current state of research in carbon-based nanomaterials, particularly the one-dimensional (1-D) forms, carbon nanotubes (CNTs) and graphene nanoribbons (GNRs), whose promising electrical, thermal, and mechanical properties make them attractive candidates for next-generation integrated circuit (IC) applications. After summarizing the basic physics of these materials, the state of the art of their interconnect-related fabrication and modeling efforts is reviewed. Both electrical and thermal modeling and performance analysis for various CNT- and GNR-based interconnects are presented and compared with conventional interconnect materials to provide guidelines for their prospective applications. It is shown that single-walled, double-walled, and multiwalled CNTs can provide better performance than that of Cu. However, in order to make GNR interconnects comparable with Cu or CNT interconnects, both intercalation doping and high edge-specularity must be achieved. Thermal analysis of CNTs shows significant advantages in tall vias, indicating their promising application as through-silicon vias in 3-D ICs. In addition to on-chip interconnects, various applications exploiting the low-dimensional properties of these nanomaterials are discussed. These include chip-to-packaging interconnects as well as passive devices for future generations of IC technology. Specifically, the small form factor of CNTs and reduced skin effect in CNT interconnects have significant implications for the design of on-chip capacitors and inductors, respectively.      

Effect of gamma irradiation on the low-frequency (1/̷) noise of linear ics: Reliability physics study

Linear integrated circuits IC 709 and 741 were irradiated by gamma rays using cobalt-60 source. Low-frequency noise was measured for these ICs before and after irradiation dose levels 10⁴, 10⁵, 10⁶ and 5 × 10⁶ R. In general IC 741s appeared to be more noisy than IC 709s. The noise levels increase substantially in the case of IC 741 after gamma irradiation of 10⁶ R. Comparative measurement results are presented in this article. These results may be useful to correlate radiation as a defect producing stress, mode and type of failures and reliability of linear ICs.     

A novel switchable pin method for regulating power in chip-multiprocessor

Transistor scaling has allowed a large number of circuits to be integrated into integrated circuit (IC) chips implemented in nanometer CMOS technology nodes. However, dark silicon which signifies for under-utilized circuitry will become dominant in future chips due to limited thermal design power (TDP). Furthermore, large voltage loss due to complex routing and placement will also degrade the performance of ICs. In addition, effectively managing power dissipation in a packaged chip is one of the major issues of IC design. Previous work done by our group mainly focused on RCL simulation and elementary IC simulation, this work not only builds on power delivery network (PDN), but also designs switchable pin working for two cores at the layout level. The essence of our idea is to supply power to the chip using traditional I/O pads. In order to balance power supply and I/O bandwidth, we set several groups of parallel switchable pins between the core and memory such that I/O pads can dynamically switch between two modes which are data transmission and power supply. To remove the risk that large current going through I/O pad breaks down the pad frame, we redesigned traditional I/O pad to operate in bi-direction. Using TSMC CMOS 180 nm process for the design and simulation, our test results show that the proposed switchable pin can well compensate voltage loss in chip multiprocessor, and transfer time of two modes is very short. For data transmission, we perform a sensitivity study to explore the impact brought by switchable pins. Our simulation results demonstrate that performance degradation is in acceptable range when the switchable pins are added to the chip-multiprocessor.     

Investigation of defect on copper bond pad surface in copper/low k process integration

In this work, inspection tools and surface analysis instruments were used to inspect and to analyze the defects at copper bond pads fabricated with copper/low k dual damascene deep submicron interconnect process integration. The defects at level are believed to be responsible for metal peeling at the Ta + Al and copper interface observed during chip wire bonding operation. The analysis results of the trace defects’ chemical composition show that the trace defects are the remainder of dielectric materials of passivation layer that is deposited on the top of the chip for protection. Copper oxide is also found to be present at the copper bond pads surface. A clear copper bond pad surface could be obtained using optimized dielectric pad window opening plasma etching conditions with suitable level plasma etching power and some overetch, improved photoresist stripping with oxygen and wet clean recipe with some chemicals. A clear copper bond pad surface will contribute to obtainment higher adhesion and lower contact resistance at Ta + Al and copper pad interface.     

考虑温度因素的3D芯片TSV容错结构设计

相比于2D芯片,3D芯片具有更高的功率密度和更低的热导率。针对散热问题,多层3D芯片一般采用具有较高热导率的铜填充硅通孔(TSV)。为提高3D芯片的成品率,在温度条件限制下,对3D芯片进行TSV的容错结构设计非常重要。分析了带有TSV的3D芯片温度模型,提出了3D芯片温度模型的TSV修复方法。根据温度要求设计总的TSV数,将这些TSV分为若干个组,每组由m个信号TSV和n个冗余TSV组成,实现了组内和组间信号的TSV修复。实验结果表明,该TSV容错结构不仅有较高修复效率,而且具有较好散热效果。     

Bed of Nails—100- $mu$m-Pitch Wafer-Level Interconnections Process

The rapid advances in integrated chip (IC) design and fabrication continue to challenge electronic packaging technology, in terms of fine pitch, high performance, low cost, and reliability. Demand for higher input/output (I/O) count per IC chip increases as the IC chip fabrication technology is continuously moving towards nano ICs with feature size less than 90 nm. As micro systems continue to move towards high speed and microminiaturization technologies, stringent electrical and mechanical properties are required. To meet the above requirements, chip-to-substrate interconnection technologies with less than 100-mum pitch are required. Currently, the coefficient of thermal expansion (CTE) mismatch between the Si chip and the substrate serves as the biggest bottleneck issue in conventional chip to substrate interconnections technology, which becomes even more critical as the pitch of the interconnects is reduces. Further, the assembly yield of such fine-pitch interconnections also serves as one of the biggest challenges. Bed-of-nails (BoN) interconnects show great potential in meeting some of these requirements for next-generation packaging. In the present study, BoN interconnects prepared by a novel process called copper column wafer-level packaging is presented. The BoN interconnect technology is being developed to meet fine pitch of 100 mum and high-density interconnections. These BoN interconnects are demonstrated by designing a test chip of 10times10mm²size with 3338 I/Os and fabricated using an optimized process. The board-level reliability tests performed under temperature cycling in the range of -40degC to 125degC show promising results.     

Direct gold and copper wires bonding on copper

The key to bonding to copper die is to ensure bond pad cleanliness and minimum oxidation during wire bonding process. This has been achieved by applying a organic coating layer to protect the copper bond pad from oxidation. During the wire bonding process, the organic coating layer is removed and a metal to metal weld is formed. This organic layer is a self-assembled monolayer. Both gold and copper wires have been wire-bonded successfully to the copper die even without prior plasma cleaning. The ball diameter for both wires are 60 μm on a 100 μm fine pitch bond pad. The effectiveness of the protection of the organic coating layer starts from the wafer dicing process up to the wire bonding process and is able to protect the bond pad for an extended period after the first round of wire bond process. In this study, oxidization of copper bond pad at different packaging processing stages, dicing and die attach curing, have been explored. The ball shear strength for both gold and copper ball bonds achieved are 5 and 6 g/mil² respectively. When subjected to high temperature storage test at 150 °C, the ball bonds formed by both gold and copper wire bond on the organic coated copper bondpad are thermally stable in ball shear strength up to a period of 1440 h. The encapsulated daisy chain test vehicle with both gold and copper wires bonding have passed 1000 cycles of thermal cycling test (−65 to 150 °C). It has been demonstrated that orientation imaging microscopy technique is able to detect early levels of oxidation on the copper bond pad. This is extremely important in characterization of the bondability of the copper bond pad surface.     

Optimization and validation of thermal management for a RF front-end SiP based on rigid-flex substrate

This paper mainly presents a new 3D stacking RF System-in-Package (SiP) structure based on rigid-flex substrate for a micro base station, with 33 active chips integrated in a small package of 5cm × 5.5cm × 0.8cm. Total power consumption adds up to 20.1 Watt. To address thermal management and testability difficulties of this RF SiP, a thermal test package is designed with the same package structure and assembly flow, only replacing active chips with thermal test dies (TTDs). Optimization and validation of thermal management for the thermal test package is conducted. Effects of the structure, chip power distribution, and ambient temperature aspects on the thermal performance are studied. Thermal vias designed in the organic substrate provide a direct heat dissipation path from TTDs to the top heatsink, which minimizes junction temperature gap of the top substrate from 31.2 °C to 5.3 °C, and enables junction temperatures of all the chips on the face to face structure to be well below 82 °C. Chip power distribution optimization indicates placing high power RF parts on the top rigid substrate is a reasonable choice. The ambient temperature optimizes with forced air convection and cold-plate cooling method, both of which are effective methods to improve thermal performances especially for this micro base station application where environment temperature may reach more than 75 °C. The thermal management validation is performed with a thermal test vehicle. Junction temperatures are compared between finite-volume-method (FVM) simulation and thermal measurement under the natural convection condition. The accordance of simulation and measurement validates this thermal test method. Junction temperatures of typical RF chips are all below 80 °C, which shows the effectiveness of thermal management of this RF SiP.     

DDFSGEN

This paper presents a functional compiler for the automatic design of Direct Digital Frequency Synthesizer (DDFS) integrated circuits (ICs) using a ROM based table look-up architecture. The compiler allows the user to specify high-level specifications such as the acceptable spurious response and it generates the IC architecture, floorplan, and layout. To construct the layout for different specifications, a library of parameterized macrocells has been developed in 1.2 m CMOS technology.A test chip with a quadrature DDFS module has been generated, using the compiler, and fabricated. The chip has two input signals: one is for frequency control while the other is for phase initialization. Input and output word lengths are 16 bits and 6 bits respectively. The chip complexity is approximately 12,000 transistors (DDFS core) and the die size is 4.8×2.9mm ². A maximum sample rate of 80 MHz has been attained implying a maximum sine (cosine) output frequency of 40 MHz and a frequency resolution of 1.22 kHz. The maximum spurious level measured is –46 dB.     

Failure analysis of pad-height effects in the fine-pitch interconnection of the anisotropic conductive films

This study analyzes the effect of the upper-to-lower pad-height ratio on the global failure probability of IC/substrate assemblies packaged using Anisotropic Conductive Film (ACF). In modeling the failure of the IC/substrate package, the probability of an opening failure in the vertical gap between the pads is calculated using a Poisson function, while the probability of a bridging failure between the pads in the pitch direction is computed using a modified box model. The opening and bridging probabilities are then combined using probability theory to establish an overall failure prediction model for the IC/substrate assembly. The results show that the failure probability increases as the sum of the lower pad height and upper pad height increases, or as the ratio R_h of the upper pad height to the lower pad height increases. Furthermore, for a given gap size between the IC device and the substrate, the minimum failure probability is obtained when the ratio of the upper pad height to the lower pad height has a value of R_h = 1. Overall, the results suggest that the reliability of ACF-packaged IC/substrate assemblies can be improved by reducing the total height of the two pad arrays or by utilizing pad arrays with an equivalent height.     

Ag/Ai schottky contacts on n-InP

Schottky contacts have been fabricated onn- InP using a Ag/Al/InP configuration where the Ag and Al thicknesses are 1000 and 40-50Å, respectively. Diodes fabricated on InP substrates withn ≈ 7 x 10¹⁶ cm_-3, have effective barrier heights, Ø_beff, of 0.4 eV and reverse bias leakage current densities of >4 A/cm² atV _r = - 3V. Appropriate heat treating at temperatures between 400–500° C raises barrier heights by as much as 0.25 eV, resulting in Ø_beff ≈ 0.65 eV and reverse bias leakage current densities less than 0.002 A/cm². Diode characteristics are found to vary dramatically with different surface preparations prior to metallization; results of x-ray photoelectron spectroscopy (XPS) and Auger electron spectroscopy (AES) depth profiling studies indicate that native oxides which are predominantly InPO₄ produce superior contacts and that aluminum first reacts with the native oxide and then migrates through the silver to the free metal surface which results in the dramatic improvements observed upon annealing.     

High Performance RF Passive Integration on a Si Smart Substrate for Wireless Applications

To achieve cost and size reductions, we developed a low cost manufacturing technology for RF substrates and a high performance passive process technology for RF integrated passive devices (IPDs). The fabricated substrate is a conventional 6“ Si wafer with a 25 μm thick SiO₂ surface. This substrate showed a very good insertion loss of 0.03 dB/mm at 4 GHz, including the conductive metal loss, with a 50 Ω coplanar transmission line (W=50 μm, G=20 μm). Using benzo cyclo butene (BCB) interlayers and a 10 μm Cu plating process, we made high Q rectangular and circular spiral inductors on Si that had record maximum quality factors of more than 100. The fabricated inductor library showed a maximum quality factor range of 30‐120, depending on geometrical parameters and inductance values of 0.35‐35 nH. We also fabricated small RF IPDs on a thick oxide Si substrate for use in handheld phone applications, such as antenna switch modules or front end modules, and high‐speed wireless LAN applications. The chip sizes of the wafer‐level‐packaged RF IPDs and wire‐bondable RF IPDs were 1.0‐1.5 mm² and 0.8‐1.0 mm², respectively. They showed very good insertion loss and RF performances. These substrate and passive process technologies will be widely utilized in hand‐held RF modules and systems requiring low cost solutions and strict volumetric efficiencies.     

Retina‐Motivated CMOS Vision Chip Based on Column Parallel Architecture and Switch‐Selective Resistive Network

A bio‐inspired vision chip for edge detection was fabricated using 0.35 μm double‐poly four‐metal complementary metal‐oxide‐semiconductor technology. It mimics the edge detection mechanism of a biological retina. This type of vision chip offer several advantages including compact size, high speed, and dense system integration. Low resolution and relatively high power consumption are common limitations of these chips because of their complex circuit structure. We have tried to overcome these problems by rearranging and simplifying their circuits. A vision chip of 160×120 pixels has been fabricated in 5×5 mm² silicon die. It shows less than 10 mW of power consumption.