共查询到18条相似文献,搜索用时 171 毫秒
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随着多级单元(Multi-Level Cell,MLC)闪存存储密度的增加,单元间干扰(Cell-to-Cell Interference, CCI)成为影响NAND闪存可靠性的主要噪声。在深入研究MLC闪存模型和CCI噪声模型基础上,提出了一种多精度感知的MLC闪存的比特翻转译码方法,该方法通过提高MLC闪存单元感知精度进而得到MLC单元中存储比特的准确对数似然比信息,利用此信息可降低原始错误比特率并且提高比特翻转译码算法的译码性能。仿真结果表明,在MLC闪存信道条件下,高感知精度下的比特翻转译码算法性能明显优于低感知精度下的性能。 相似文献
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随着多级单元(Multi-Level Cell,MLC)闪存存储密度的增加,单元间干扰(Cell-to-Cell Interference,CCI)成为影响NAND闪存可靠性的主要噪声。在深入研究MLC闪存模型和CCI噪声模型的基础上,提出了一种MLC闪存的CCI噪声均衡化算法。该算法通过估计CCI干扰强度进而对感知MLC阈值电压进行补偿,可以更准确地读取MLC单元中存储的信息。仿真结果表明,在MLC闪存信道条件下,CCI噪声均衡化算法可以有效减少相邻状态的阈值电压交叉现象,有助于降低原始比特错误率,增强MLC闪存的可靠性。 相似文献
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传统的串行抵消比特翻转(SCF)译码算法仅用对数似然比(LLR)的绝对值去衡量信息比特译码结果的可靠情况,导致误块率(BLER)过高和翻转的尝试次数较多。提出一种串行抵消比特翻转译码算法PLR-SCF,分析SC译码算法发生错误译码的原因,通过仿真观察LLR、极化信道可靠度和信息位所在的位置与SC译码算法发生首个判决错误之间的关系,并利用上述因素设计一个能准确衡量信息位发生译码错误程度的度量公式。仿真结果表明,相对于传统的SCF译码算法,该算法能够有效降低BLER,特别是在高信噪比下获得的最大信噪比增益约为0.12 dB,翻转尝试次数与SCF减少13.6%。 相似文献
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为了提高非规则LDPC码译码的收敛速度,提出了一种具有快速收敛速度的LDPC码构造算法。该算法在原有非规则LDPC码的基础上,通过对校验矩阵进行列重排,来提升信息比特译码的可靠性,以此降低迭代次数,提高收敛速度。仿真实验表明,采用该算法设计的LDPC码,在采用基于变量节点的分层置信度传播(VL-BP)译码算法下,平均迭代次数有明显的降低。另外,对于置信度传播(BP)译码算法和VL-BP译码算法来说,设计的LDPC码具有更优的误码性能。 相似文献
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在加性高斯白噪声(additive white Gaussian noise,AWGN)信道下极化码的串行抵消(successive cancellation,SC)译码方法计算是在对数似然比(log likelihood ratio,LLR)域进行的,◢f◣函数节点的计算采用基于双曲正切规则的和积算法。针对双曲正切函数和反双曲正切函数提出了折线逼近算法,将这两个函数分别简化为9段折线函数;为了得到折线逼近算法下更优异的误帧率性能,编码前在信息比特中添加了16位CRC。仿真结果表明,针对码长◢为N=1024、信息位长度为K◣=496的极化码,提出的改进算法比和积算法有更好的误帧率性能且降低了译码复杂度,提高了译码速度。 相似文献
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为了减少在低信噪比区的平均迭代次数和削弱LLR(Logarithm Likelihood Ratio, LLR)值的振荡,分析了中短码长LDPC码错误帧对应校验节点对数似然比及校验和变化的规律,提出了一种基于消息振荡及校验更新的改进BP译码算法。该算法通过提前结束迭代译码的准则来减少在低信噪比区的平均迭代次数,并通过修正校验节点的更新来削弱LLR值的振荡来提高译码性能。仿真结果表明,相对于BP算法:在低信噪比区,该算法减少了平均迭代次数且译码性能没有损失;而在中高信噪比区,其提高了译码性能而平均迭代次数无需增加。 相似文献
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在IEEE802.16e通信标准的LDPC码背景下,基于LDPC码的软判决LLR BP译码算法,结合LDPC码的最小和处理方式和硬判决译码思想,针对译码性能和复杂程度提出了一种改进的BP译码算法。在相同信噪比条件下,新BP算法在译码性能上非常接近LLR BP算法,同时其复杂程度却远小于LLR BP算法,提高了工程可实现性。 相似文献
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为减小低密度奇偶校验(LDPC)码的量化译码算法的实现复杂度,提出了一种改进的4比特量化自适应偏移最小和(AOMS)译码算法。改进的AOMS译码算法中引入了预设的固定迭代次数作为启动偏移量修正因子自适应选择的条件;设计了一种4比特非均匀数据量化方案,保证量化数据的取值范围既能较好地满足外信息的动态范围,又能简单实现优化的量化偏移量修正因子。仿真结果表明,与浮点译码算法相比较,改进的量化AOMS译码算法的译码性能损失较小。 相似文献
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Haochuan Song Jen-Chien Fu Shih-Jia Zeng Jin Sha Zaichen Zhang Xiaohu You Chuan Zhang 《中国科学:信息科学(英文版)》2018,61(10):102307
With the ever-growing storage density, high-speed, and low-cost data access, flash memory has inevitably become popular. Multi-level cell (MLC) NAND flash memory, which can well balance the data density and memory stability, has occupied the largest market share of flash memory. With the aggressive memory scaling, however, the reliability decays sharply owing to multiple interferences. Therefore, the control system should be embedded with a suitable error correction code (ECC) to guarantee the data integrity and accuracy. We proposed the pre-check scheme which is a multi-strategy polar code scheme to strike a balance between reasonable frame error rate (FER) and decoding latency. Three decoders namely binary-input, quantized-soft, and pure-soft decoders are embedded in this scheme. Since the calculation of soft log-likelihood ratio (LLR) inputs needs multiple sensing operations and optional quantization boundaries, a 2-bit quantized hard-decision decoder is proposed to outperform the hard-decoded LDPC bit-flipping decoder with fewer sensing operations. We notice that polar codes have much lower computational complexity compared with LDPC codes. The stepwise maximum mutual information (SMMI) scheme is also proposed to obtain overlapped boundaries without exhausting search. The mapping scheme using Gray code is employed and proved to achieve better raw error performance compared with other alternatives. Hardware architectures are also given in this paper. 相似文献
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Multi-level cell (MLC) flash memory has lower bit cost compared to single-level cell (SLC) flash memory. However, there are several obstacles to the wide use of MLC flash memory, including slow write performance and shorter lifespan. To improve the performance and lifespan of MLC flash memory, we propose an FTL (flash translation layer) for MLC flash memory, called ComboFTL. By exploiting the SLC mode of MLC flash memory, ComboFTL manages a small SLC region for hot data and a large MLC region for cold data. To provide the performance and lifespan similar to those of SLC flash memory, ComboFTL identifies the hotness/coldness of data effectively. It can also adjust its several policies based on workload changes. Our experimental results showed that ComboFTL improves the write performance and lifespan of MLC flash memory significantly. 相似文献
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短低密度校验(LDPC)码的Tanner图中通常存在环路,变量节点之间的信息不再相互独立,导致LLR BP算法译码性能的下降。针对上述问题,提出一种改进型LLR BP译码算法,推导出有环时变量节点的真实信息,利用最小均方误差准则计算出有记忆的变量节点信息的权值,通过调整变量节点信息的迭代过程降低变量节点之间信息的相关性。仿真结果表明,改进型LLR BP算法具有比LLR BP算法、归一化BP算法及偏移量BP算法更好的LDPC译码性能。 相似文献
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为了弥补UMP BP-Based相对于LLR BP译码算法的性能缺陷,提出一种改进型UMP BP-Based译码算法。通过将Normalized BP-Based和Offset BP-Based译码算法的优点相结合,并利用最小均方误差准则来计算该算法中的参数。仿真结果表明,在相同误码率的情况下,改进型UMP BP-Based译码算法比UMP BP-Based、Normalized BP-Based以及Offset BP-Based具有更好的LDPC译码性能。 相似文献
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Recently, Multi-Level Cell (MLC) NAND flash memory is becoming widely used as storage media for mobile devices such as mobile phones, MP3 players, PDAs and digital cameras. MLC NAND flash memory, however, has some restrictions that hard disk or Single-Level Cell (SLC) NAND flash memory do not have. Since most traditional database techniques assume hard disk, they may not provide the best attainable performance on MLC NAND flash memory. In this paper, we design and implement an MLC NAND flash-based DBMS for mobile devices, called AceDB Flashlight, which fully exploits the unique characteristics of MLC NAND flash memory. Our performance evaluations on an MLC NAND flash-based device show that the proposed DBMS significantly outperforms the existing ones. 相似文献
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为了弥补UMP BP-Based译码算法相对于LLR BP译码算法的性能缺陷,提出一种改进型UMP BP-Based译码算法.该算法中的参数是在最小均方误差准则下确定的,对所有的LDPC码的译码具有通用性.仿真结果表明,在相同误码率的情况下,改进型UMP BP-Based译码算法比UMP BP-Based译码算法、Normalized BP-Based译码算法以及Offset BP-Based译码算法具有更好的LDPC译码性能. 相似文献