VLSI implementation of a neural network model

The authors describe a complementary metal-oxide-semiconductor (CMOS) very-large-scale integrated (VLSI) circuit implementing a connectionist neural-network model. It consists of an array of 54 simple processors fully interconnected with a programmable connection matrix. This experimental design tests the behavior of a large network of processors integrated on a chip. The circuit can be operated in several different configurations by programming the interconnections between the processors. Tests made with the circuit working as an associative memory and as a pattern classifier were so encouraging that the chip has been interfaced to a minicomputer and is being used as a coprocessor in pattern-recognition experiments. This mode of operation is making it possible to test the chip's behavior in a real application and study how pattern-recognition algorithms can be mapped in such a network     

Optoelectronic winner-take-all VLSI shunting neural network

In this paper we present an analog winner-take-all MOS VLSI (metal-oxide semiconductor/very large scale integration) optoelectronic network. By varying either the input current or circuit parameters, the circuit can evidence several different behaviors such as contrast enhancement, strict winner-take-all, or winner-take-all with hysteresis. Simulation and experimental results from the prototype circuit are also discussed.     

An analog VLSI recurrent neural network learning a continuous-timetrajectory

Real-time algorithms for gradient descent supervised learning in recurrent dynamical neural networks fail to support scalable VLSI implementation, due to their complexity which grows sharply with the network dimension. We present an alternative implementation in analog VLSI, which employs a stochastic perturbation algorithm to observe the gradient of the error index directly on the network in random directions of the parameter space, thereby avoiding the tedious task of deriving the gradient from an explicit model of the network dynamics. The network contains six fully recurrent neurons with continuous-time dynamics, providing 42 free parameters which comprise connection strengths and thresholds. The chip implementing the network includes local provisions supporting both the learning and storage of the parameters, integrated in a scalable architecture which can be readily expanded for applications of learning recurrent dynamical networks requiring larger dimensionality. We describe and characterize the functional elements comprising the implemented recurrent network and integrated learning system, and include experimental results obtained from training the network to represent a quadrature-phase oscillator.     

Toward a general-purpose analog VLSI neural network with on-chiplearning

This paper describes elements necessary for a general-purpose low-cost very large scale integration (VLSI) neural network. By choosing a learning algorithm that is tolerant of analog nonidealities, the promise of high-density analog VLSI is realized. A 64-synapse, 8-neuron proof-of-concept chip is described. The synapse, which occupies only 4900 mum(2) in a 2-mum technology, includes a hybrid of nonvolatile and dynamic weight storage that provides fast and accurate learning as well as reliable long-term storage with no refreshing. The architecture is user-configurable in any one-hidden-layer topology. The user-interface is fully microprocessor compatible. Learning is accomplished with minimal external support; the user need only present inputs, targets, and a clock. Learning is fast and reliable. The chip solves four-bit parity in an average of 680 ms and is successful in about 96% of the trials.     

脉频调制神经网络VLSI的设计及应用

本文提出了一种用于故障诊断识别的改进脉冲频率调制(PFM)VLSI神经网络电路,改进了传统的基于软件的机械故障诊断模式,发挥了神经网络超大规模集成电路(VLSI)的优势.利用单层感知器网络、场效应管电路实现了一种新的数字模拟混合突触乘法/加法器电路,而且该神经网络电路的突触权值不需要学习调整,降低了电路的复杂性.以此电路为基础,设计了进行主轴承噪声故障诊断的神经网络故障识别系统.将含有故障信息的原始噪声信号,经过前置信号处理分析、故障特征值提取和神经网络运算,得出VLSI电路输出端电容的电压——代表待识别信号与模板故障信号的“欧氏距离”,进而判断出故障的类别.经过仿真测试,基于硬件的诊断系统的识别性能接近于基于软件的系统.     

An analog VLSI implementation of Hopfield's neural network

The basic requirements for electronic implementations of the fully connected Hopfield network are examined, highlighting the reasons why the authors regard analog implementations as more appropriate. Analog VLSI networks are then discussed, with particular reference to the selection of memory points and the design of the synapse, and experimental results are given. A test chip containing 14 neurons and 196 synapses is described     

A programmable analog VLSI neural network processor forcommunication receivers

An analog VLSI neural network processor was designed and fabricated for communication receiver applications. It does not require prior estimation of the channel characteristics. A powerful channel equalizer was implemented with this processor chip configured as a four-layered perceptron network. The compact synapse cell is realized with an enhanced wide-range Gilbert multiplier circuit. The output neuron consists of a linear current-to-voltage converter and a sigmoid function generator with a controllable voltage gain. Network training is performed by the modified Kalman neuro-filtering algorithm to speed up the convergence process for intersymbol interference and white Gaussian noise communication channels. The learning process is done in the companion DSP board which also keeps the synapse weight for later use of the chip. The VLSI neural network processor chip occupies a silicon area of 4.6 mmx6.8 mm and was fabricated in a 2-mum double-polysilicon CMOS technology. System analysis and experimental results are presented.     

Two digital circuits for a fully parallel stochastic neural network

This paper presents two digital circuits that allow the implementation of a fully parallel stochastic Hopfield neural network (SHNN). In a parallel SHNN with n neurons, the n*n stochastic signals s (ij) pulse with probability which are proportional to the synapse inputs, are simultaneously available. The proposed circuits calculate the summation of the stochastic input pulses to neuron i(F(i)=Sigma(j) s(ij)). The resulting network achieves considerable speed up with respect to the previous network.     

Automatic target recognition using a neocognitron

The use of a neocognitron in an automatic target recognition (ATR) system is described. An image is acquired, edge detected, segmented, and centered on a log-spiral grid using subsystems not discussed in the paper. A conformal transformation is used to map the log-spiral grid to a computation plane in which rotations and scalings are transformed to displacements along the vertical and horizontal axes, respectively. Since the neocognitron can recognize shifted objects, the use of log-spiral images by the neocognitron enables the system to recognize scaled, rotated, and translated objects. Two modifications to prior neocognitron implementations are described. A new weight reinforcement method is introduced which solves a significant training problem for the neocognitron. A method of reducing training time is also introduced which specifies the initial layer of weights in the network. All subsequent layers are trained using unsupervised learning. Simulation results using 32×32 and 64×64 intercontinental ballistic missile (ICBM) images are presented     

VLSI implementation of transcendental function hyperbolic tangent for deep neural network accelerators

Extensive use of neural network applications prompted researchers to customize a design to speed up their computation based on ASIC implementation. The choice of activation function (AF) in a neural network is an essential requirement. Accurate design architecture of an AF in a digital network faces various challenges as these AF require more hardware resources because of its non-linear nature. This paper proposed an efficient approximation scheme for hyperbolic tangent (tanh) function which purely based on combinational design architecture. The approximation is based on mathematical analysis by considering maximum allowable error in a neural network. The results prove that the proposed combinational design of an AF is efficient in terms of area, power and delay with negligible accuracy loss on MNIST and CIFAR-10 benchmark datasets. Post synthesis results show that the proposed design area is reduced by 66% and delay is reduced by nearly 16% compared to state-of-the-art.     

VLSI architectures for neural networks

An introduction to neural networks and neural information processing is provided. Neurocomputers are discussed, focusing on how their design exploits the architectural properties of VLSI circuits. General-purpose and special-purpose neurocomputer developments throughout the world are examined. As illustration, and to put European developments in perspective, some of the important projects in the United States and Japan are described. European research is then discussed in greater detail     

基于RBF神经网络的模拟数字信号调制识别

针对多种信号在低信噪比条件下识别率低的问题,利用高阶累积量良好的抑制噪声特性,通过构造高阶累积量作为特征参数之一,并联合其他特征参数,采用优化的径向基神经网络对模拟数字信号进行自动调制识别。Matlab仿真表明,该种方法能够有效提高低信噪比条件下的信号识别率。     

基于BP神经网络的数字式光照度计设计

设计了一种基于BP神经网络和硅光电池的宽量程、高精度数字式光照度计,并详细介绍了这种光照度计的工作原理、软硬件设计以及数据拟合的过程.实验数据表明,该光照度计量程宽、精度高,完全能够满足农作物生长环境检测的应用要求.     

基于神经网络的灰度级数字水印嵌入技术

提出一种将灰度级数字水印嵌入到彩色图像中的方法。利用DCT变换,先将灰度水印编码成二值位流信息：用神经网络建立彩色图像中所选择的像素之间关系模型。最后,通过调整被选择像素点与模型输出值之间大小关系来嵌入水印的二值位流信息。采用信息放大技术,加强水印的嵌入强度。利用神经网络、DCT反变换,提取灰度水印。实验结果表明,该算法对目前JPEG图像压缩变换和某些图像处理操作具有极强的鲁棒性。     

VLSI technologies for artificial neural networks

VLSI systems, basic integrated circuits, and silicon technologies are discussed. Novel circuit and design principles that provide a foundation for the implementation of a wide variety of neural network models in silicon are described. The key issues for a successful integration of neural systems are identified. The realization of algorithms in silicon is examined. Special-purpose hardware for carrying out the activation and transfer function and for the connection elements is discussed. A brief overview of the current silicon technologies is provided     

Employee turnover: a neural network solution

In today's working environment, a company's human resources are truly the only sustainable competitive advantage. Product innovations can be duplicated, but the synergy of a company's workforce cannot be replicated. It is for this reason that not only attracting talented employees but also retaining them is imperative for success. The study of employee turnover has attempted to explain why employees leave and how to prevent the drain of employee talent. This paper focuses on using a neural network (NN) to predict turnover. If turnover can be found to be predictable the identification of at-risk employees will allow us to focus on their specific needs or concerns in order to retain them in the workforce. Also, by using a Modified Genetic Algorithm to train the NN we can also identify relevant predictors or inputs, which can give us information about how we can improve the work environment as a whole. This research found that a NNSOA trained NN in a 10-fold cross validation experimental design can predict with a high degree of accuracy the turnover rate for a small mid-west manufacturing company.     

MART: a multichannel ART-based neural network

This paper describes MART, an ART-based neural network for adaptive classification of multichannel signal patterns without prior supervised learning. Like other ART-based classifiers, MART is especially suitable for situations in which not even the number of pattern categories to be distinguished is known a priori; its novelty lies in its truly multichannel orientation, especially its ability to quantify and take into account during pattern classification the different changing reliability of the individual signal channels. The extent to which this ability can reduce the creation of spurious or duplicate categories (a major problem for ART-based classifiers of noisy signals) is illustrated by evaluation of its performance in classifying QRS complexes in two-channel ECG traces which were taken from the MIT-BIH database and contaminated with noise.     

Image labelling: a neural network approach

The solution of the image labelling problem using the emerging computational paradigm of neural networks is shown. A brief introduction to neural network technology is provided. The labelling problem is formulated as a problem in symbolic constraint satisfaction. Alternative solution methods are cited. A Hopfield neural network structure which embodies the labelling constraints is developed in detail. The procedure to determine the energy function and interconnection weight is described. Experimental results and network convergence properties are analysed. Future research diections are outlined.     

VLSI implementation of pulsating neural networks

We describe a generic approach for realizing networks of pulsating neurons based on charge pumping of interface states situated in the channel of MOS transistors. Two basic building blocks will be described: the pulse activated charge pumping (PSCP) synapse, and the charge sensitive oscillator (CSO). The PSCP synapse which operates as either a short or a long term memory device which produces a charge packet proportional to the number of pulses applied to its input, will be described in detail together with experimental results demonstrating its capability. The CSO circuit which is a charge controlled oscillator will be described together with simulations of its output frequency dependence on its input voltage, and the relation between the temporal dependence of output waveform on its input charge.