A 0.13μm CMOS Δ ∑ fractional-N frequency synthesizer for WLAN transceivers

A fractional-N frequency synthesizer fabricated in a 0.13μm CMOS technology is presented for the application of IEEE 802.11 b/g wireless local area network(WLAN) transceivers.A monolithic LC voltage controlled oscillator(VCO) is implemented with an on-chip symmetric inductor.The fractional-TV frequency divider consists of a pulse swallow frequency divider and a 3rd-order multistage noise shaping(MASH)△Σmodulator with noise-shaped dithering techniques.Measurement results show that in all channels,phase noise of the synthesizer achieves -93 dBc/Hz and -118 dBc/Hz in band and out of band respectively with a phase-frequency detector (PFD) frequency of 20 MHz and a loop bandwidth of 100 kHz.The integrated RMS phase error is no more than 0.8°.The proposed synthesizer consumes 8.4 mW from a 1.2 V supply and occupies an area of 0.86 mm~2.     

A 55 nm CMOS △∑fractional-N frequency synthesizer for WLAN transceivers with low noise filters

A fully integrated ΔΣ fractional-N frequency synthesizer fabricated in a 55 nm CMOS technology is presented for the application of IEEE 802.11b/g wireless local area network(WLAN) transceivers.A low noise filter,occupying a small die area,whose power supply is given by a high PSRR and low noise LDO regulator,is integrated on chip.The proposed synthesizer needs no off-chip components and occupies an area of 0.72 mm2 excluding PAD.Measurement results show that in all channels,the phase noise of the synthesizer achieves -99 dBc/Hz and -119 dBc/Hz in band and out of band respectively with a reference frequency of 40 MHz and a loop bandwidth of 200 kHz.The integrated RMS phase error is no more than 0.6°.The proposed synthesizer consumes a total power of 15.6 mW.     

A 900 MHz fractional-N synthesizer for UHF transceiver in 0.18μm CMOS technology

A 900 MHz fractional-N synthesizer is designed for the UHF transceiver. The VCO with a 4 bits capacitor bank covers 823–1061 MHz that implements 16(24)sub-bands. A 7/8 dual-modulus prescaler is implemented with a phase-switching circuit and high-speed flip–flops, which are composed of source coupled logic. The proposed synthesizer phase-locked loop is demonstrated with a 50 k Hz band width by a low 12.95 MHz reference clock, and offers a better phase noise and band width tradeoff. To reduce the out-band phase noise, a 4-levels 3-order single-loop sigma–delta modulator is applied. When its relative frequency resolution is settled to 10-6, the testing results show that the phase noises are –120.6 d Bc/Hz at 1 MHz and –95.0 d Bc/Hz at 100 k Hz. The chip is2.1 mm2 in UMC 0.18μm CMOS. The power is 36 m W at a 1.8 V supply.     

A △∑ fractional-N frequency synthesizer for FM tuner using low noise filter and quantization noise suppression technique

A △∑ fractional-N frequency synthesizer fabricated in a 130 nm CMOS technology is presented for the application of an FM tuner. A low noise filter, occupying a small die area and decreasing the output noise, is integrated on a chip. A quantization noise suppression technique, using a reduced step size of the frequency divider, is also adopted. The proposed synthesizer needs no off-chip components and occupies an area of 0.7 mm2. The in-band phase noise （from 10 to 100 kHz） below -108 dBc/Hz and out-of-band phase noise of -122.9 dBc/Hz （at 1 MHz offset） are measured with a loop bandwidth of 200 kHz. The quantization noise suppression technique reduces the in-band and out-of band phase noise by 15 dB and 7 dB respectively. The integrated RMS phase error is no more than 0.48°. The proposed synthesizer consumes a total power of 7.4 mW and the frequency resolution is less than 1 Hz.     

A fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system in 0.13μm CMOS

This paper proposes a sigma-delta fractional-N frequency synthesizer-based multi-standard I/Q carrier generation system.With reasonable frequency planning,the system can be used in multi-standard wireless communication applications(GSM,WCDMA,GPRS,TD-SCDMA,WLAN(802.11a/b/g)).The implementation is achieved by a 0.13μm RF CMOS process.The measured results demonstrate that three quadrature VCOs(QVCO) continuously cover the frequency from 3.1 to 6.1 GHz(65.2%),and through the successive divide-by-2 prescalers to achieve the frequency from 0.75 to 6.1 GHz continuously.The chip was fully integrated with the exception of an off-chip filter.The entire chip area is only 3.78 mm~2,and the system consumes a 21.7 mA@1.2 V supply without output buffers.The lock-in time of the PLL frequency synthesizer is less than 4μs over the entire frequency range with a direct frequency presetting technique and the auxiliary non-volatile memory(NVM)can store the digital configuration signal of the system,including presetting signals to avoid the calibration process case by case.     

A power scalable PLL frequency synthesizer for high-speed △-∑ ADC

A 35-130 MHz/300-360 MHz phase-locked loop frequency synthesizer for △-∑ analog-to-digital con- verter （ADC） in 65 nm CMOS is presented. The frequency synthesizer can work in low phase-noise mode （300-360 MHz） or in low-power mode （35-130 MHz） to satisfy the ADC＇s requirements. To switch between these two modes, a high frequency GHz LC VCO followed by a divided-by-four frequency divider and a low frequency ring VCO followed by a divided-by-two frequency divider are integrated on-chip. The measured results show that the fre- quency synthesizer achieves a phase-noise of-132 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 1.12 ps with 1.74 mW power consumption from a 1.2 V power supply in low phase-noise mode. In low-power mode, the frequency synthesizer achieves a phase-noise of-112 dBc/Hz at 1 MHz offset and an integrated RMS jitter of 7.23 ps with 0.92 mW power consumption from a 1.2 V power supply.     

A transformer-loaded receiver front end for 2.4 GHz WLAN in 0.13μm CMOS technology

A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented.Based on zero-IF receiver architecture,the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer.As the load of the LNA,the on-chip transformer is optimized for lowest resistive loss and highest power gain.The whole front end draws 21 mA from 1.2 V supply,and the measured results show a double side band noise figure of 3.75 dB,-31 dBm IIP3 with 44 dB conversion gain at maximum gain setting.Implemented in 0.13μm CMOS technology,it occupies a 0.612 mm~2 die size.     

Design of a dual-channel multi-mode GNSS receiver with a∑△fractional-N synthesizer

A 72 mW highly integrated dual-channel multimode GNSS(global navigation satellite system) receiver with aΣ△fractional-N synthesizer which covers GPS L1 and the Compass B1/B2/B3 band is presented.This chip was fabricated in a TSMC CMOS 0.18μm process and packaged in a 48-pin 3×3 mm~2 land grid array chip scale package.This work achieves NF≤5.3 dB without an external LNA,channel gain = 105 dB for channel one (Compass B2 and B3 band),and channel gain = 110 dB for channel two(GPS L1 and Compass B1 band).Image rejection(IMRR) = 36 dB,phase noise is -115.9 dBc @ 1 MHz and -108.9 dBc @ 1 MHz offset from the carrier for the two channels separately.At the low power consumption,multibands of GNSS are compatible in one chip, which is easy for consumers to use,when two different navigation signals are received simultaneously.     

0.13μm超高性能CMOS晶体管

据日本《电子材料》2 0 0 0年第 2期报道 ,三菱电机公司开发了超高性能的 0 .1 3μm CMOS晶体管。该产品栅长为 0 .1 3μm,在电源电压 1 .8V下达到了目前最高的电流驱动能力 ( n沟道晶体管为 81 0 μA/μm,p沟道晶体管为 42 0 μA/μm)。此外 ,实现了每 1单位电路 1 2 ps的迟延速度 (电路中包含晶体管自身的寄生电容 )。这一器件的开发成功将大大推进大容量数据高速处理系统 L SI的规模生产。0.13μm超高性能CMOS晶体管@孙再吉     

A 5 Gb/s transceiver in 0.13μm CMOS for PCIE2.0

This paper presents a CML transceiver for a PCI-express generation 2 physical layer protocol that has been fabricated by SMIC’s 0.13μm CMOS technology.The active area of the transceiver is 0.016 mm~2 and it consumes a total of 150 mW power at a 1.2 V supply voltage.The transmitter uses two stage pre-emphasis circuits with active inductors,reducing inter-symbol interference and extended bandwidth;the receiver uses a time-domain adaptive equalizer,the circuit uses an inductive peaking technique and extends the bandwidth,and the use of active inductors reduces the circuit area and power consumption effectively.The measurement results show that this circuit could stably transmit the signal at the data rate of 5 Gbps,the output signal swing of the transmitter is 350 mV with jitter of 14 ps,the eye opening of the receiver is 135 mV and the eye width is 0.56 UI.The circuit performance sufficiently meets the requirements of the PCI-Express 2.0 protocol.     

0.13μm CMOS工艺抗辐射触发器优化设计

随着体硅CMOS工艺尺寸不断减小、集成度不断提高,电路受到单粒子辐射效应的影响会变得越来越严重。在大尺寸工艺条件下常用的DICE结构触发器结构,在受到单粒子效应影响后,会产生一定脉宽的扰动并传输至下一级,对整个电路的可靠性产生影响。为消除上述影响,采用了C单元结构对触发器的输出端口进行优化设计,将原有的一个结点输出结构优化为利用两个互补的存储结点作为C单元结构的输入。利用仿真手段对优化后的结构进行验证,证明了优化后的结构有很好的抗扰动能力,同时通过优化版图设计,提升触发器结构的抗辐射能力。经过此次对触发器的优化设计,为今后超深亚微米抗辐射电路的设计提供了借鉴。     

A 1.78–3.05?GHz fractional-N frequency synthesizer with power reduced multi-modulus divider

Nowadays, multi-band frequency synthesizers are very popular for their compatibility, which lowers the chip cost. In this article, a low power 2.4?GHz broadband fractional-N frequency synthesizer based on ???C?? modulation is presented. A novel power reduced multi-modulus divider based on 2/3 divider cells is presented. The ??mod?? signals are employed to dynamically control the current of the end-of-cycle logic blocks in 2/3 divider cells. When the end-of-cycle logic blocks have no contribution to the divider operation, they are turned off to save power. The saved power is more than 30% in the desired division ratio range. A dual-band voltage controlled oscillator with switched capacitor arrays is designed to cover a wide tuning range. Other circuits such as phase frequency detector, charge pump and loop filter are also integrated on the chip. The whole frequency synthesizer has been fabricated in Chartered 0.18???m RF CMOS process. Tested results show it covers the tuning range from 1.78 to 3.05?GHz, with phase noise smaller than ?85 dBc/Hz at 100?kHz offset, and smaller than ?115 dBc/Hz at 3?MHz offset. Its power consumption is only 9.2?mW under 1.8?V supply voltage, and the chip occupies an area of 1.2?mm?×?1.3?mm.     

基于0.13μm CMOS的WiFi功率放大器设计

基于TSMC 0.13 μm CMOS工艺,设计了一款适用于无线保真(WiFi)收发机的发射端、工作在2.4 GHz且增益可控的三级级联功率放大器.驱动级采用单管结构,后两级采用共源共栅(MOSFET)结构.利用调节共源共栅晶体管栅极的电容来改变栅极电压的相位,进而弥补了共源共栅结构的劣势,增加了整个系统的线性度和增益.另外,使用外部数字信号控制每级偏置的大小来适应不同的输出需求.整个结构采用电源电压:第一级为1.8V,后两级为3.3V,芯片面积为1.93 mm×1.4 mm.利用Candence Spectre RF软件工具对所设计的功率放大器进行仿真.结果表明,在2.4 GHz的工作频点,功率放大器的饱和输出功率为24.9 dBm,最大功率附加效率为22％,小信号增益达到28 dB.     

An instant-switching ?–Σ fractional-N frequency synthesizer with adjustable duty cycles

A Phase-Locked Loop (PLL)-based frequency synthesizer (FS) with adjustable duty cycle is presented. By employing digital processing circuitry and the ??C?? fractional-N technique, the FS is capable of generating arbitrary frequencies in a wide frequency range, and capable of adjusting the clock duty cycles. In addition, the switching between different frequencies is instant except when a very fine frequency resolution is required. The adjustable duty cycle and instant switching are desired features in applications such as time-interleaved Analog-to-Digital-Converters (ADCs), switched-capacitor circuits, and DC?CDC converters. The design was fabricated using a 0.13???m CMOS process. This paper gives the theories, analysis, implementation, and measurement results of this FS.     

0.13μm CMOS芯片上窄脉冲成型电路

本文将脉冲功率领域中基于脉冲成型线的窄脉冲产生技术运用于芯片电路设计中,基于0.13μm的CMOS工艺,进行片上电路设计与实现.用CadenceTM Spectre Simulation进行了原理图和版图仿真分析,选用标准的片上共面波导(CPW)作为脉冲成型线(PFL),采用NMOS晶体管作为开关,仿真结果表明在共面波...     

A wideband 0.13 μm CMOS LC-VCO for IMT-advanced and UWB applications

This paper presents an LC voltage controlled oscillator(VCO) in a dual-band frequency synthesizer for IMT-advanced and UWB applications.The switched current source,cross-coupled pair and noise filtering technique are adopted in this VCO design to improve the performance of the phase noise,power consumption,voltage amplitude,and tuning range.In order to achieve a wide tuning range,a reconfigurable LC tank with 4 bits switch control is adopted in the core circuit design.The size of the entire chip with pad is 1.11 0.98 mm2.The test results show that the current dissipation of the VCO at UWB and IMT-Advanced band is 3 mA and 4.5 mA in a 1.2 V supply.The tuning range of the designed VCO is 3.86-5.28 GHz and 3.14-3.88 GHz.The phase-noise at 1 MHz frequency offset from a 3.5 GHz and 4.2 GHz carrier is-123 dBc/Hz and-119 dBc/Hz,respectively.     

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

We present an integrated fractional-N low-noise frequency synthesizer for satellite applications. By using two integrated VCOs and combining digital and analog tuning techniques, a PLL lock range from 8 to 12 GHz is achieved. Due to a small VCO fine tuning gain and optimized charge pump output biasing, the phase noise is low and almost constant over the tuning range. All 16 sub-bands show a tuning range above 900 MHz each, allowing temperature compensation without sub-band switching. This makes the synthesizer robust against variations of the device parameters with process, supply voltage, temperature and aging. The measured phase noise is ?87 dBc/Hz and ?106 dBc/Hz at 10 kHz and 1 MHz offset, respectively. In integer-N mode, phase noise values down to ?98 dBc/Hz at 10 kHz and ?111 dBc/Hz at 1 MHz offset, respectively, were measured.