Estimate Threshold Voltage Shift in a-Si:H TFTs Under Increasing Bias Stress

A method of estimating threshold voltage shift in hydrogenated amorphous silicon (a-Si:H) transistors under increasing bias stress is proposed. Although the threshold voltage shift in a-Si:H thin-film transistor (TFT) has been modeled well under constant bias stress, its property with increasing bias stress, which occurs in many a-Si:H-based compensating circuits, still cannot be quantified without any restriction, such as constant overdrive bias or short stressing time. In this paper, we propose a model which is effective under an arbitrary increasing stress for a prolonged time. The proposed model reduces to the constant bias model if the stress bias remains unchanged. With this method, the lifetime of most compensating circuits based on a-Si devices can be estimated completely.      

有机薄膜晶体管阈值电压漂移现象的研究

研究了有机薄膜晶体管(Oganic thin film transistor，OTFT)的阈值电压漂移与栅偏置电压和偏置时间的关系、不同栅绝缘膜对OTFT阈值电压漂移的影响以及不同栅绝缘膜MIS结构的C-V特性。结果发现．栅偏置电压引起了OTFT转移特性曲线的平移而场效应迁移率(μFE)和亚阈值陡度(△S)不变；阈值电压漂移的量与偏置时间的对数呈线性关系。还发现阈值电压漂移量与栅绝缘膜绝缘性能有关，绝缘性能好的绝缘膜(如SiO2)器件阈值电压漂移量小．绝缘性能差的绝缘膜(如TaOx)器件阈值电压漂移量大。认为有机晶体管阈值电压漂移是由沟道载流子以直接隧穿方式进入栅绝缘膜内的陷阱造成的。     

Observation of Threshold-Voltage Instability in Single-Crystal Silicon TFTs on Flexible Plastic Substrate

We report the first observation of threshold-voltage instability of single-crystal silicon (Si) thin-film transistors (TFTs) that are fabricated on low-temperature flexible plastic substrate. Single-crystal Si of 200-nm thickness is transferred from silicon-on-insulator (SOI) onto an indium-tin-oxide-coated polyethylene terephthalate host substrate after selectively removing the buried-oxide layer from the SOI. TFTs of n-type were then fabricated on the transferred single-crystal Si layer with 1.8-mum thick SU-8-2 epoxy as the gate dielectric layer. It is observed that the threshold voltage (V_th) of these TFTs shifts to higher and lower values under high positive and negative gate-voltage stress, respectively. A logarithmic time-dependence of the V_th shift at high bias stress was clearly indicated. These results suggest that the instability of the threshold voltage of the single-crystal Si TFTs is attributed to the charge trapping in the gate dielectric layer.     

基于CMOS阈值电压的基准电路设计

在数/模混合集成电路设计中电压基准是重要的模块之一.针对传统电路产生的基准电压易受电源电压和温度影响的缺点,提出一种新的设计方案,电路中不使用双极晶体管,利用PMOS和NMOS的阚值电压产生两个独立于电源电压和晶体管迁移率的负温度系数电压,通过将其相减抵消温度系数,从而得到任意大小的零温度系数基准电压值.该设计方案基于某公司0.5 μm CMOS工艺设计,经HSpice仿真验证表明,各项指标均已达到设计要求.     

阈值电压波动初探

阈值电压（Vth)是液晶材料最重要的参数之一，主要根据液晶显示屏的驱动方式来设计。合适的Vth是LCD显示质量的重要保障，在制造和生产过程中，要尽量保证它的一致性。避免器件出现对比度不良或串扰等现象。结合生产过程中的实际情况及经常出现的问题，阐述了阈值电压的影响因数及设计使用中的注意事项。     

GaAs MESFET的漏源电压对旁栅阈值电压的影响

研究了改变ＭＥＳＦＥＴ漏源电压大小和交流源漏电极对旁栅阈值电压的影响,并从理论上解释了与高场下衬底深能级ＥＬ２的碰撞电离关系。     

EEPROM工艺中场开启电压的特殊要求与对策

ＥＥＰＲＯＭ要求场开启电压≥２０Ｖ，Ｐ－Ｎ结击穿电压也要求≥２０Ｖ，前者需提高场区杂质浓度，而后者则需要降低场杂质浓度，通过工艺模拟和实验找到了一种化解这个矛盾的对策，首先根据Ｐ－Ｎ结击穿电压的要求确定场区杂质浓度，继而大幅度调节场氧厚度，从而使二者都能满足要求。     

一种基于阈值电压的新型基准电压源设计

SOC及智能功率集成电路对基准电压源提出了很高的要求。基于阈值电压和BiCMOS工艺,设计了一种新型的电流模式基准电压源。利用NMOS管阈值电压的线性负温度系数产生CTAT电压,与一种常见的PTAT电压相加,产生了对温度不敏感的基准电压。电路基于TSMC0.5μm BiCMOS工艺,采用Cadence Spectre对电路的各项性能进行了仿真验证。仿真结果表明,在宽温度范围(-40℃到120℃)内温度系数为9×10-6/℃,基准电压值为951mV。     

表面极化对阈值电压和饱和电压的影响

考虑挠曲电极化,但不考虑界面上离子选择吸附产生的极化,文章详细讨论了表面极化P_s对平行向列液晶盒阈值电压和饱和电压的影响。文章由自由能的角度推导得到指向矢n倾角θ满足的微分方程和相应的边界条件;推导得到约化阈值电压u_(tn)和约化饱和电压u_(sat)的方程;讨论了约化表面极化强度P对约化阈值电压u_(th)和约化饱和电压u_(sat)的影响,并绘图表示,数值计算表明,表面极化对向列液晶盒的影响主要表现在界面锚定。     

Threshold voltage, field effect mobility, and gate-to-channelcapacitance in polysilicon TFTs

Based on experimental and theoretical studies of n- and p-channel polysilicon thin film transistors with gate W/L ratios from 0.3 to 3.3, we have demonstrated that the threshold voltage extracted from gate to channel capacitance data results in field effect mobility parameters which are independent of device geometry. The parameters extracted using this V_t allow us to reproduce the I-V characteristics of the n- and p channel TFTs over wide ranges of bias voltages and gate sizes. The C_gc-V_GS characteristics of polysilicon TFTs are strongly affected by the trapping and de-trapping of carriers. As a result, the measured C_gc characteristic is a function of measurement frequency and gate length. However, we demonstrate that to the first order, the frequency dispersion of the C_gc curve can be related to the effective carrier transit time determined using the V_GS dependent field effect mobility     

动态阈值nMOSFET阈值电压随温度退化特性

对动态阈值nMOSFET阈值电压随温度退化特性进行了一阶近似推导和分析。动态阈值nMOSFET较之普通nMOSFET,降低了阈值电压温度特性对温度、沟道掺杂浓度及栅氧厚度等因素的敏感程度。讨论了动态阈值nMOSFET优秀阈值电压温度特性的内在机理。动态阈值nMOSFET优秀的阈值电压随温度退化特性使之非常适合工作于高温恶劣环境。     

光照对阈值电压均匀性的影响

研究了光照对砷化镓阈值电压均匀性的影响.结果表明光照使耗尽型MESFET器件的沟道电流增大,使阈值电压向负方向增加,并提高了阈值电压的均匀性.研究认为砷化镓单晶材料的深能级缺陷是影响MESFET阈值电压均匀性的重要因素之一,而光照在一定程度上减弱了这一影响.     

光照对阈值电压均匀性的影响

研究了光照对砷化镓阈值电压均匀性的影响.结果表明光照使耗尽型MESFET器件的沟道电流增大,使阈值电压向负方向增加,并提高了阈值电压的均匀性.研究认为砷化镓单晶材料的深能级缺陷是影响MESFET阈值电压均匀性的重要因素之一,而光照在一定程度上减弱了这一影响.     

Effects of mechanical strain on TFTs on spherical domes

In this paper, amorphous-silicon (a-Si:H) thin-film transistors (TFTs) were fabricated on a plastic substrate, which was then permanently deformed into a spherical dome shape after the device fabrication process. The TFTs were patterned in an island structure to prevent cracking in the device films during the substrate deformation. In the majority of the TFTs, the off-current and gate leakage current do not change substantially. Depending on the island structure, the electron mobility either increased or decreased after deformation. This change in mobility was correlated with the mechanical strain in the device islands determined by finite element modeling of the deformation process. Tensile strain caused slightly higher mobility in planar structures. In a mesa-type structure, silicon films on top of the pillars could be in compression after the dome deformation, leading to a slight decrease in mobility.     

N管开启电压调整注入对P－N结击穿电压的影响

为了讨论问题方便，定义了两种Ｐ－Ｎ结：“漏Ｐ－Ｎ结”和“单纯Ｐ－Ｎ结”。分析了二者击穿电压相关因素的差别，认为“漏Ｐ－Ｎ结”的击穿电压与沟道区杂质浓度密切相关。ＥＥＰＲＯＭ的研制中，要求“漏Ｐ－Ｎ结”击穿电压≥２０Ｖ，即沟道区杂质浓度要低到一定的程度，而同时又必须保证一定的开启电压，即沟道区杂质浓度要高到一定的程度。通过分析与实验，提出了解决这一矛盾的通用原则。     

功率VUMOSFET器件阈值电压最佳化设计

从功率VUMOSFET器件结构出发,通过使用模拟软件SILVACO进行工艺和器件仿真,根据仿真结果分析了器件沟道掺杂浓度分布对阈值电压的影响,进而提出工艺改进的措施.对功率VUMOSFET的设计与生产具有指导意义.     

EEPROM中浮栅MOS晶体管阈值电压的研究

重点讨论了在斜波脉冲条件下，EEPROM中fiotox管在浮栅充电放电过程中阈值电压的变化，对原有模型进行了补充，修正，所得结果与实验相符。     

共面转换液晶盒的阈值电压

本文从连续体理论出发，给出了强锚定和弱锚定边界条件下，有预倾角时IPS型盒的阈值电压的解析结果。阈值电压随着锚定能的减小而减小，随着预倾角的增大而增大。     

隐埋层中二维效应对全耗尽SOI非对称HALO结构阈值电压的影响

在非对称HALO结构的全耗尽SOI二维阈值电压解析模型的基础上,对阈值电压受隐埋层中二维效应的影响进行了讨论.通过与一维模型的比较,说明在深亚微米SOI MOSFET器件中隐埋层的二维效应会导致器件提前出现短沟道效应.新模型结果与二维数值模拟软件MEDICI吻合较好.     

隐埋层中二维效应对全耗尽SOI非对称HALO结构阈值电压的影响

在非对称HALO结构的全耗尽SOI二维阈值电压解析模型的基础上,对阈值电压受隐埋层中二维效应的影响进行了讨论.通过与一维模型的比较,说明在深亚微米SOI MOSFET器件中隐埋层的二维效应会导致器件提前出现短沟道效应.新模型结果与二维数值模拟软件MEDICI吻合较好.