共查询到20条相似文献,搜索用时 15 毫秒
1.
Yo-Sheng Lin Kai-Siang Lan Ming-Yuan Chuang Yu-Ching Lin 《International Journal of Electronics》2018,105(6):1063-1077
This paper reports a 94 GHz CMOS voltage-controlled oscillator (VCO) using both the negative capacitance (NC) technique and series-peaking output power and phase noise (PN) enhancement technique. NC is achieved by adding two variable LC networks to the source nodes of the active circuit of the VCO. NMOSFET varicaps are adopted as the required capacitors of the LC networks. In comparison with the conventional one, the proposed active circuit substantially decreases the input capacitance (Cin) to zero or even a negative value. This leads to operation (or oscillation) frequency (OF) increase and tuning range (TR) enhancement of the VCO. The VCO dissipates 8.3 mW at 1 V supply. The measured TR of the VCO is 91~96 GHz, close to the simulated (92.1~96.7 GHz) and the calculated one (92.2~98.2 GHz). In addition, at 1 MHz offset from 95.16 GHz, the VCO attains an excellent PN of – 98.3 dBc/Hz. This leads to a figure-of-merit (FOM) of ?188.5 dBc/Hz, a remarkable result for a V- or W-band CMOS VCO. The chip size of the VCO is 0.75 × 0.42 mm2, i.e. 0.315 mm2. 相似文献
2.
Kossel M. Buchmann P. Menolfi C. Morf T. Schmatz M. Toifl T. Weiss J. 《Electronics letters》2005,41(19):1053-1054
A 10 GHz multiphase phase-locked loop (PLL) implemented in 90 nm bulk CMOS technology is presented that uses a bootstrapped NMOS inverter oscillator to obtain steeper clock edges, which may yield an improved jitter performance. The measured values for the rms and peak-to-peak jitter are better than 1 and 7 ps, respectively. 相似文献
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提出了一种新的两级环形振荡器结构,通过控制PMOS的衬底电压,来降低PMOS管的阈值电压,从而使新的环形振荡器可以在低电压下工作到很高的频率。仿真结果表明,在电源电压为1V,调节电压在0~1V范围内变化时,振荡器的频率为300MHz-4GHz。 相似文献
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设计了一款3.7 GHz宽带CMOS电感电容压控振荡器.采用了电容开关的技术以补偿工艺、温度和电源电压的变化,并对片上电感和射频开关进行优化设计以得到最大的Q值.电路采用和舰0.18 μm CMOS混合信号制造工艺,芯片面积为0.4 mm×1 mm.测试结果显示,芯片的工作频率为3.4~4 GHz,根据输出频谱得到的相位噪声为-100 dBc/Hz@1 MHz,在1.8 V工作电压下的功耗为10 mW.测试结果表明,该VCO有较大的工作频率范围和较低的相位噪声性能,可以用于锁相环和频率合成器. 相似文献
5.
LI En-ling WANG Xue SONG Lin-hong YUAN Yong-xia YU Fa-da LIU Man-cang 《中国邮电高校学报(英文版)》2009,16(3):103-107
A voltage controlled oscillator (VCO) module is designed, which can be used for the third generation mobile communication (3G) system. The circuit is simulated by spectre radio frequency (RF) by TSMC 0.25 μm CMOS process. During the simulation, the performance parameters of the designed VCO are as follows: tuning range 1.804 GHz-2.039 GHz, phase noise - 136.457 dBc/Hz @1 MHz, - 146.045 dBc/Hz@3 MHz, supply voltage 2.5 V, voltage output rate of 0.8 V-2.6 V, power consumption 25 mW. The layout of the related circuit is drawn by the Virtuoso Layout Editor. 相似文献
6.
A 50 GHz cross-coupled voltage controlled oscillator(VCO) considering the coupling effect of inductors based on a 65 nm standard complementary metal oxide semiconductor(CMOS) technology is reported.A pair of inductors has been fabricated,measured and analyzed to characterize the coupling effects of adjacent inductors. The results are then implemented to accurately evaluate the VCO’s LC tank.By optimizing the tank voltage swing and the buffer’s operation region,the VCO achieves a maximum efficiency of 11.4%by generating an average output power of 2.5 dBm while only consuming 19.7 mW(including buffers).The VCO exhibits a phase noise of—87 dBc/Hz at 1 MHz offset,leading to a figure of merit(FoM) of-167.5 dB/Hz and a tuning range of 3.8%(from 48.98 to 50.88 GHz). 相似文献
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提出了一种应用于10 Gb/s高速串并接口电路(Serdes)的高性能锁相环。采用正交压控振荡器(QVCO)实现4路等相位间隔的5 GHz时钟,输出采用2分频单转差缓冲器,实现可忽略相差的8路等相位间隔的2.5 GHz时钟。电荷泵中采用负反馈技术,以提高电流匹配性能。在SMIC 40 nm工艺下完成设计,在 1.1 V的供电电压下,锁相环的总电流为7.6 mA,输出5 GHz时钟在10 kHz~100 MHz积分范围内的均方根抖动约为107 fs,芯片尺寸仅为780 μm×410 μm。 相似文献
8.
2.5GHz低相位噪声CMOS LC VCO的设计 总被引:3,自引:2,他引:3
用0 .35μm、一层多晶、四层金属、3.3V的标准全数字CMOS工艺设计了一个全集成的2 .5 GHz L C VCO,电路采用全差分互补负跨导结构以降低电路功耗和减少器件1/ f噪声的影响.为了减少高频噪声的影响,采用了在片L C滤波技术.可变电容采用增强型MOS可变电容,取得了2 3%的频率调节范围.采用单个16边形的对称片上螺旋电感,并在电感下加接地屏蔽层,从而减少芯片面积,优化Q值.取得了在离中心频率1MHz处- 118d Bc/ Hz的相位噪声性能.电源电压为3.3V时的功耗为4 m A. 相似文献
9.
A 10-GHz CMOS ring oscillator that employs a multi-pass technique for boosting its frequency is proposed in this paper. The
proposed circuit allows the tuning gain to be lowered by deploying the coarse/fine frequency tuning whilst maintaining wide
frequency coverage. The small signal model of the proposed delay stage and the circuit operation are discussed in this paper.
The time-variant analysis presented permits accurate prediction of the frequency tuning characteristic and the results have
been verified by simulation. The phase noise analysis is also discussed in detail to provide better insight to the noise that
is contributed by each transistor. The calculated results agreed well with that of the simulations.
Hai Qi Liu was born in Jiangsu, China, in 1979. He received the B.S. and M.Sc. degrees, both in electrical engineering from the Tianjin
University, Tianjin, China, in 2000, and Tongji University, Shanghai, China, in 2003, respectively. He is currently working
toward the Ph.D. degree at the Nanyang Technological University, Singapore. His research focuses mainly on the design of fully
integrated oscillators and Phase-Locked Loops for optical communication applications. His research interests also include
RF frequency synthesizers and RF front-end designs for wireless applications.
Wang Ling Goh obtained both her B.Eng and Ph.D. degrees from the department of Electrical and Electronic Engineering at the Queen’s University
of Belfast (QUB) in United Kingdom. When working on her Ph.D., she was also engaged as a research associate at the Northern
Ireland Semiconductor Research Centre (NISRC) at QUB. Dr Goh joined the School of Electrical and Electronic Engineering at
the Nanyang Technological University (NTU) in Singapore as a lecturer in January 1996. She is now an Associate Professor in
the Division of Circuits and Systems, School of Electrical & Electronic Engineering. Dr Goh has to-date co-authored 1 book,
filed 13 patents (granted), and published about 60 research papers in international conferences and journals. Her research
interests are in areas of silicon device processing technologies as well as digital and mixed-signal IC designs.
Liter Siek received the B.A.Sc. degree from University of Ottawa, Ontario, Canada; the M.Eng.Sc. from University of New South Wales,
Sydney, Australia; and the Ph.D. from Nanyang Technological University, Singapore. From 1981 to 1983 he was employed in several
companies in the area of automation and control. From 1983 to 1985, he was with SGS, currently known as ST Microelectronics
situated in Castelletto, Milan, Italy, where he worked in the central R&D Laboratories for Linear IC. From 1985 to 1987, he
was with the same company situated in Singapore’s Asia Pacific Design Center. Since October 1988, he has been with Nanyang
Technological University. His research interests are in the design of bipolar, CMOS and BiCMOS analog/mixed signal ICs. In
addition, he has authored and co-authored 53 international journal/conference technical papers. 相似文献
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A gated ring oscillator(GRO) based time-to-digital converter(TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2.The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm~2.According to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency. With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 MHz.Under a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency. 相似文献
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设计了一种全差分高速环形压控振荡器(VCO).该VCO有三级,每一级的增益是快慢通路增益的矢量叠加和,快慢通路的增益由底部电流源决定,差分控制电压通过镜像电流源控制快慢通路的各自电流,最终实现对振荡频率的调节.分析了VCO的工作原理及其相位噪声.电路采用TSMC公司0.18μm标准CMOS工艺制作.测试结果显示:芯片工作频率为10.88~11.72GHz,相位噪声为-101dBc/Hz@10MHz,输出信号抖动为3.8ps rms,在1.8V电源电压下的直流功耗约为75mW.该VCO可以应用于锁相环和频率合成器中. 相似文献
14.
In this paper, a low phase noise and low power 5.15?GHz LC-tank VCO is presented and analysed. The phase noise achieved is??91,??116 and??126?dBc/Hz at 100?KHz, 1?MHz and 3?MHz offsets respectively from the carrier frequency of 5.15?GHz, with 1.8?V power supply voltage and giving a very low power consumption of about 2.5?mW by considering the proposed oscillator topology, which consumes less power than the classical oscillator using the traditional differential transconductor pair. A broad tuning range has been achieved by means of standard mode PMOS varactors. The tunability of the designed VCO covers 530?MHz, from 4.78?GHz up to 5.31?GHz. Predicted performance has been verified by analyses and simulations using ELDO-RF tool with 0.35?µm CMOS TSMC parameters. 相似文献
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研究了一种用于微处理器时钟同步PLL的高带宽低噪声的压控振荡器(VCO),该VCO采用了交叉耦合的电流饥饿型环形振荡器,通过改善其控制电压变换电路,大大拓宽了压控增益的线性范围,消除了振荡器对控制电压的影响,降低了输出时钟的相位噪声.基于CSMC 3.3 V 0.35 μm CMOS工艺的仿真结果表明,取延迟单元沟道长度为1 μm、中心频率为365 MHz时,压控增益为300 MHz/V,其线性区覆盖范围是30~700 MHz,在偏离中心频率600 kHz处的相位噪声为-95 dB/Hz,低频1/f噪声在-20 dB/Hz以下.该VCO可以通过适当减小延迟单元沟道长度来拓宽压控增益线性范围. 相似文献
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《Solid-State Circuits, IEEE Journal of》2005,40(11):2203-2211
We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver realized in a 90 nm digital CMOS process. Wide and precise linear frequency tuning is achieved through digital control of a large array of standard n-poly/n-well MOSCAP devices that operate in flat regions of their C- V curves. The varactors are partitioned into binary-weighted and unit-weighted banks that are sequentially activated during frequency locking and tracking. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz high-band output. To attenuate the quantization noise to below the natural oscillator phase noise, the varactors undergo high-speed second-order /spl Sigma//spl Delta/ dithering. We analyze the effect of the /spl Sigma//spl Delta/ dithering on the phase noise and show that it can be made sufficiently small. The measured phase noise at 20 MHz offset in the GSM900 band is -165 dBc/Hz and shows no degradation due to the /spl Sigma//spl Delta/ dithering. The 3.6 GHz DCO core consumes 18.0 mA from a 1.4 V supply and has a very wide tuning range of 900 MHz to support the quad-band operation. 相似文献
20.
设计了一款用于中国60 GHz标准频段的射频接收前端电路。该射频接收前端采用直接变频结构,将59~64 GHz的微波信号下变频至5~10 GHz的中频信号。射频前端包括一个四级低噪声放大器和电流注入式的吉尔伯特单平衡混频器。LNA设计中考虑了ESD的静电释放路径。后仿真表明,射频接收前端的转换增益为13.5~17.5 dB,双边带噪声因子为6.4~7.8 dB,输入1 dB压缩点为-23 dBm。电路在1.2 V电源电压下功耗仅为38.4 mW。该射频接收前端电路采用IBM 90 nm CMOS工艺设计,芯片面积为0.65 mm2。 相似文献