Impact of Microwave Interference on Dynamic Operation and Power Dissipation of CMOS Inverters

The effects of electromagnetic interference (EMI) from high-power microwave signals on CMOS inverters are reported. In order to study these effects more effectively, a novel analytical parameter extraction method, which allows us to predict the dynamic operation of the inverters under interference from experimentally measured load-line characteristics, is developed. Based on the method, the output voltages, output short-circuit currents, propagation delays, and dynamic power dissipation during EMI were extracted. The results showed that the inverters suffer severely from compressed output voltage swing, bit errors, significant changes in the propagation delays, and substantially increased short-circuit currents, as well as a large increase in dynamic power dissipation during logic state transition from high to low and vice versa. Scaling down of the inverters showed that such operational parameters of the devices were more strongly affected by the interference, resulting in significantly more vulnerable CMOS inverters.     

A generalized tanh law MOSFET model and its applications to CMOSinverters

A generalized tanh law model is proposed to simulate the current-voltage characteristics of both long-channel and short-channel MOS transistors. The proposed model is used to calculate the propagation delay, short-circuit power dissipation, and logic threshold voltage of CMOS inverters. The results obtained are in good agreement with those obtained using classical models     

Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits

A simple formula is derived for quick calculation of the maximum short-circuit dissipation of static CMOS circuits. A detailed discussion of this short-circuit dissipation is given based on the behavior of the inverter when loaded with different capacitances. It was found that if each inverter of a string is designed in such a way that the input and output rise and fall times are equal, the short-circuit dissipation will be much less than the dynamic dissipation (<20%). This result has been applied to a practical design of a CMOS driving circuit (buffer), which is commonly built up of a string of inverters. An expression has also been derived for a tapering factor between two successive inverters of such a string to minimize parasitic power dissipation. Finally, it is concluded that optimization in terms of power dissipation leads to a better overall performance (in terms of speed, power, and area) than is possible by minimization of the propagation delay.     

Circuit Design of a High Speed and Low Power CMOS Continuous-time Current Comparator

Current comparator is a fundamental component of current-mode analog integrated circuits. A novel high-performance continuous-time CMOS current comparator is proposed in this paper, which comprises one CMOS complementary amplifier, two resistive-load amplifiers and two CMOS inverters. A MOS resistor is used as the CMOS complementary amplifier's negative feedback. Because the voltage swings of the CMOS complementary amplifier are reduced by low input and output resistances, the delay time of the current comparator is shortened. Its power consumption can be reduced rapidly with the increase of input current. Simulation results based on 1.2 m CMOS process model show the speed of the novel current comparator is comparable with those of the existing fastest CMOS current comparators, and its power consumption is the lowest, so it has the smallest power-delay product. Furthermore, the new current comparator occupies small area and is process-robust, so it is very suitable to high-speed and low-power applications.     

基于恒流源的改进型压电陶瓷高压驱动电源

恒流源压电陶瓷驱动电源具有结构简单及频响好等优点,但静态功耗高是其突出缺点。该文提出了一种改进的恒流源压电陶瓷驱动电源,在静态功耗一定的情况下,提高了其动态输出能力及竞争能力。该改进型压电陶瓷驱动电源的样机具有2.4~300V的输出电压范围,在静态恒定电流为0.1A时,动态输出电流最大可达0.44A。基于恒流源的高压驱动电源,驱动电压主要由驱动管的耐压决定,原理上可得到远高于现有高压运放的水平,在高压压电陶瓷驱动方面有广阔的前景。     

Simple class-AB voltage follower with slew rate and bandwidth enhancement and no extra static power or supply requirements

A simple modification of the MOS voltage follower is introduced that provides it with efficient class-AB operation. The modified circuit has dynamic output currents and bandwidth that are essentially larger than the conventional MOS voltage follower. This is achieved with the same static power dissipation, very small additional circuit complexity and lower distortion. Experimental verification of all these characteristics is provided.     

A fully-differential OTA based on CMOS cascode inverters operating from 1-V power supply

A low voltage operating fully-differential CMOS OTA construction, which uses dual-input CMOS cascode inverters, is proposed. The OTA is a two-stage configuration with dual-input CMOS cascode inverters at the input stage, and traditional CMOS inverters in the output stage, with a common-mode feedback path from the output terminals to one of the input terminals of cascode inverters. In order to effectively reduce its threshold voltages by bulk bias technique, the OTA has been designed and fabricated by using a 0.15 μm triple-well CMOS process. The OTA successfully operated from 1-V power supply, with 59 dB of differential voltage gain, 80.9 dB of CMRR and 25 MHz of unity gain frequency, at 60 μA of current consumption.     

High-performance low-power CMOS memories using silicon-on-sapphire technology

Complementary MOS silicon-on-sapphire inverters fabricated using silicon-gate technology and 5-/spl mu/m channel-length devices has achieved nanosecond propagation delays and picojoule dynamic power-x delay products. In addition to high switching speed and low dynamic power, inverters with low leakage currents and therefore low quiescent power have been obtained. Two complex CMOS/SOS memories that realize the performance attributes of the individual inverters have been fabricated. An aluminium-gate 256-bit fully decoded static random-access memory features a typical access time of 50 ns at 10 V with a power dissipation of 0.4 /spl mu/W/bit (quiescent) and 10 /spl mu/W/bit (dynamic). The access time at 5 V is typically 95 ns. A silicon-gate 256-bit dynamic shift register features operation at clock signals of 200 MHz at 10 V and 75 MHz at 5 V. The dynamic power dissipation at 50 MHz and 5 V is typically 90 /spl mu/W/bit.     

A 1.5-V current-mode CMOS sample-and-hold IC with 57-dB S/N at 20MS/s and 54-dB S/N at 30 MS/s

A new video-speed current-mode CMOS sample-and-hold IC has been developed. It operates with a supply voltage as low as 1.5 V, a signal-to-noise ratio (S/N) of 57 dB and 54 dB with a 1-MHz input signal at clock frequencies of 20 and 30 MHz, and a power dissipation of 2.3 mW. It consists of current-mirror circuits with the node voltages at the input and the output terminals which are kept constant in all phases of the input signal by the use of low-voltage operational amplifiers; this reduces the signal current dependency. The low-voltage operational amplifier consists of a MOS transistor and a constant current source in a common-gate amplifier configuration. Only two analog switches in differential form were used to construct the differential sample-and-hold circuit. This minimizes the error caused by the switch feed through, and thus high accuracy can be realized. Since there is no analog switch in the input path, it is possible to convert the input signal voltage to a current by simply connecting an external resistor. The circuit was fabricated using standard 0.6-μm MOS devices with normal threshold voltages (V_th) of +0.7 V (nMOS) and -0.7 V (pMOS)     

Efficient Slew-Rate Enhanced Operational Transconductance Amplifier

Today, along with the prevalent use of portable equipment, wireless, and other battery powered systems, the demand for amplifiers with a high gain-bandwidth product (GBW), slew rate (SR), and at the same time very low static power dissipation is growing. In this work, an operational transconductance amplifier (OTA) with an enhanced SR is proposed. By inserting a sensing resistor in the input port of the current mirror in the OTA, the voltage drop across the resistor is converted into an output current containing a term in proportion to the square of the voltage, and then the SR of the proposed OTA is significantly enhanced and the current dissipation can be reduced. The proposed OTA is designed and simulated with a 0.5 m complementary metal oxide semiconductor (CMOS) process. The simulation results show that the SR is 4.54 V/s, increased by 8.25 times than that of the conventional design, while the current dissipation is only 87.3%.     

Dynamic back bias CMOS driver for low-voltage applications

A high performance CMOS driver scheme for low-voltage applications is proposed. The threshold voltage of the MOS devices is electrically controlled in order to achieve high-speed operation during the transitions without increasing the static power dissipation. The V_TH control scheme has been applied to the pull-up section of the driver and simulations at 0.9 V and at 50 MHz have shown that the proposed driver exhibits a speed advantage of 40% during pull-up transitions over a conventional CMOS driver, without leading to a serious increase in the power dissipation     

Current gain high-frequency CMOS operational amplifiers

The performance of high unity gain-bandwidth current gain-based CMOS operational amplifiers fabricated in a 1.5-/spl mu/m CMOS digital process is discussed. High unity-gain bandwidth was achieved by using short-channel MOS transistors operating in the current gain mode. Stacked current mirrors have been utilized as current gain stages to minimize the effects of the channel-length modulation in short-channel MOS transistors. Open-circuit gain of 60 to 70 dB, a unity-gain bandwidth of 70 to 100 MHz, and slew-rate of 200 V//spl mu/s were demonstrated at a DC power dissipation of 1-2 mW.     

TFT-LCD驱动控制电路芯片研究

研制成功一款彩屏手机用262144色132RGB×176-dot分辨率TFT-LCD单片集成驱动控制电路芯片,提出了基于低/中/高混合电压工艺、数模混合信号VLSI显示驱动芯片的设计及其验证方法,开发了SRAM访问时序冲突解决电路、二级输出驱动电路和动态负载补偿输出缓冲电路等新型电路结构,有效减小了电路的功耗和面积,抑制了回馈电压的影响,提高了液晶显示画面质量。采用0.25μm混合电压CMOS工艺实现的工程样片一次性流片成功,整个芯片的静态功耗约为5mW,输出灰度电压的安定时间小于30μs,芯片性能指标均达到设计要求。     

A Subthreshold Low Phase Noise CMOS LC VCO for Ultra Low Power Applications

A subthreshold low power, low phase-noise voltage controlled oscillator (VCO) is demonstrated in a commercial 0.18 mum CMOS process. In subthreshold regime, MOS drain current is dominated by diffusion mechanism resulting in a high ratio of transconductance to drain current and suppressed phase noise. Therefore, low power and low phase noise characteristics are achieved without using nonconventional high passive components. The VCO measures a phase noise of -106 dBc/Hz at 400 kHz offset from 2.63 GHz oscillation frequency with 0.43 mW power dissipation drawn from 0.45 V power supply. Figures of merit for this VCO (power-frequency-normalized of 12 dB and power frequency-tuning-normalized of -10 dB) are among the best reported for CMOS oscillators.     

A Power‐Efficient CMOS Adaptive Biasing Operational Transconductance Amplifier

This paper presents a two‐stage power‐efficient class‐AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low‐power dissipation and low‐voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only 0.4 μW from a supply voltage of ±0.6 V and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class‐AB amplifier. The design is fabricated using 0.18‐μm CMOS technology.     

一种低功耗的LDO线性集成稳压器的实现

提出了一种静态功耗很低的BICMOS LD0线性集成稳压器的实现方法,详细分析了它的工作原理,并给出了具体电路、仿真波形以及分析数据。该电路的主要特点是采用一种自偏置电流基准源,有很强的电源抑制比和很好的温度特性。高电流效率的输出缓冲器,用以降低电路的静态功耗。为防止输出电压过冲,采用误差放大器与NMOS管的结构进行调节,这样保证了输出电压在输入电压上电的过程中无过冲。     

An adaptive biasing one-stage CMOS operational amplifier fordriving high capacitive loads

An adaptive biasing one-stage CMOS operational amplifier for driving high capacitive loads has been developed. The amplifier has been designed to drive liquid-crystal-displays (LCDs) in battery-supplied devices. Contradictory features like low power dissipation and high driving capability at low supply voltage are required. Complementary differential input stages provide rail-to-rail common-mode input range. With a special cross-coupled double-to-single-end conversion, a full supply output range is achieved. These improvements solve a functional problem of some existing adaptive biasing amplifiers. Simulation and measurements demonstrate good correlation and show the expected results, especially in the critical operating area     

一种电流跟踪补偿的输入输出全摆幅运算放大器

介绍了一种工作在2.5V电压下、具有全摆幅输入与输出功能的两级CMOS运算放大器。通过一种简单有效的电流跟踪电路实现了输入跨导恒定的要求，这样使得频率补偿变得容易实现；为了降低功耗，输入级工作在弱反型区：输出级采用带有前馈控制电路的AB类输出电路，实现了输出信号的轨至轨。电路具有结构简单、功耗低、面积小、性能高等优点。     

一种集成低压低功耗电流复制电路设计

本文提出了一种集成低压低功耗电流复制电路。利用单级放大器和电压跟随器构成的负反馈回路实现对输入电压跟的跟随,利用等比例电阻实现电流的等比例复制,电路结构简单,仅由5个MOS管和2个等比例电阻构成。基于TSMC 0.18μm工艺完成电路设计,使Spectre完成电路仿真。结果表明,电路电源电压为1V时,电路静态功耗仅为1μW。在输入电流范围为0-50μA时,输出电流线性跟随输入电流,当输入电流大于3μA时,电流复制精度大于99%,电路带宽为31MHz。     

一种低压高频CMOS电流乘法器的设计

提出了一种新颖的高频四象限电流乘法器电路，该乘法器使用了工作在三极管区的互补MOS器件，并且采用了饱和区MOS管的平方律特性。该电路采用0．35pmCMOS工艺，使用HSpice软件仿真。仿真结果显示，该乘法器电路在±1.18V的电源电压下工作时，静态功耗为1．18mW，-3dB带宽可达到1．741GHz。与先前的电流乘法器电路相比，工作电压降低了，带宽提高了。