Σ-Δ调制技术在小数分频器中的应用

小数分频技术解决了锁相环频率合成器中鉴相频率和输出频率分辨率的矛盾。但一般的小数分频技术引入了严重的小数杂散问题。因为Δ-Σ调制技术对噪声具有整形的作用,把Σ-Δ调制技术应用在小数分频频率合成器中,与传统的PLL(锁相环)频率合成器相比具有明显的优越性,他可以提供很宽的频率范围、极高的频率分辨率、较低的单边带相位噪声以及良好的杂散性能。     

∑-△调制技术在小数分频器中的应用

小数分频技术解决了锁相环频率合成器中鉴相频率和输出频率分辨率的矛盾。但一般的小数分频技术引入了严重的小数杂散问题。因为△-∑调制技术对噪声具有整形的作用，把∑-△调制技术应用在小数分频频率合成器中，与传统的PLL（锁相环）频率合成器相比具有明显的优越性，他可以提供很宽的频率范围、极高的频率分辨率、较低的单边带相位噪声以及良好的杂散性能。     

一种基于双环小数分频锁相的低杂散频综设计

为解决传统单环小数分频锁相电路存在的整数边界杂散的问题,该文设计了一种基于双环小数分频锁相的电路结构。设置两级锁相环,通过前级锁相环产生可变参考信号,进入后级小数锁相环进行频率合成,实现了宽带小步进、低杂散频综的设计,电路结构简单,可靠性高;同时也提高了宽带频率合成器在细步进模式下的杂散抑制能力,是一种实现宽带细步进频率合成的好方法。     

小数分频锁相环杂散抑制技术研究和应用

本文设计了一种杂散抑制方案,能较好地解决宽频段、快速换频应用中频合杂散的问题。小数分频锁相环(小数环,小数PLL)是宽频段频率合成器的主流解决方案。小数分频锁相环应用的主要问题是小数杂散问题,通过环路滤波器改善杂散会增加环路锁定时间,并且效果有限。     

∑-△调制技术在小数分频锁相环中的应用

从小数分频频率合成器中小数杂散的产生入手,分析了高阶数字∑-△调制对量化噪声的高通整型特性,从而有效地解决了小数分频锁相环的杂散问题。最后用硬件电路实现了基于∑-△调制的小数分频频率合成器,频率范围为2400-2510MHz,频率步进125kHz,在偏离主频1kHz时相位噪声优于-99dBc／Hz,换频时间小于100μs。证明了该频率合成器是一种简单实用、高性价比的频率合成器。     

基于Σ-Δ调制技术的小数分频锁相环的应用

介绍了基于Σ-Δ调制技术的小数分频的锁相环是怎样降低输出杂散的。正是因为基于Σ-Δ调制技术的小数分频与传统小数分频相比具有较低的输出杂散,应用前景广阔。通过实例分析说明在设计频率综合器时,采用小数分频替代整数分频,以达到改善相位噪声的目的。为了实现小步进,通常采用DDS+PLL,在对频率转换时间要求不高的情况,也可以用小数分频来替代。     

基于双环系统的细步进频率合成器

针对小数分频锁相的整数边带杂散问题提出了一种基于双环系统的细步进频率合成方法。根据变参考抑制小数分频整数边带杂散的工作原理,采用一级整数分频锁相环与一级小数分频锁相环级联的方法共同构成细步进频率合成系统,通过软件算法调整第一级锁相环的N分频值和M参数,最终实现全频段杂散指标最优。结果表明,根据该方法设计的宽带（带宽为4~8 GHz）、细步进（1 kHz）的频率合成器,其实测杂散优于75 dBc,相位噪声在1 kHz处优于-96 dBc/Hz,跳频时间小于47 μs     

∑-Δ调制技术在小数分频锁相环中的应用

从小数分频频率合成器中小数杂散的产生入手，分析了高阶数字∑-△调制对量化噪声的高通整型特性，从而有效地解决了小数分频锁相环的杂散问题。最后用硬件电路实现了基于∑-△调制的小数分频频率合成器，频率范围为2400～2510MHz，频率步进125kHz，在偏离主频1kHz时相位噪声优于-99dBc／Hz，换频时间小于100Fs。证明了该频率合成器是一种简单实用、高性价比的频率合成器。     

Σ-Δ调制技术在频率合成中的应用

本文介绍了采用Σ-Δ调制技术的小数分频PLL频率合成器.为了提高分频信号的质量和减少小数分频器的小数杂散,我们采用了高阶Σ-Δ调制技术原理.本文还提出了采用这种原理的具体电路实现方式.     

L波段低相噪、快锁定频率合成器研制

小数分频（FNPLL）频率合成器是近年来出现的一种新技术,它与传统的整数分频频率合成器相比具有频率分辨率高、相位噪声低、快速锁定等优点。用ANALOGDE．VICES公司的最新的小数分频锁相环频率合成器芯片ADF4193,设计了一个L波段锁相环频率合成器。文章系统地阐述了ADF4193的组成、工作原理,使用ADISimPLL软件进行环路滤波器设计,通过仿真得到各种性能指标,并对仿真结果和改变参数避开杂散的方法进行了详细分析。通过测试,结果证明了ADF4193组成的频率合成器具有优良的性能。     

A fractional spur suppression technique in the fractional-N frequency synthesizer

A fractional spur suppression technique is presented based on the principle of spur generation, which makes the phase between the divider output and the reference be permanently coherent like integer-N frequency synthesizer, so a real lock is achieved. The spurious tones are strongly reduced without sacrificing the PLL bandwidth. The detailed scheme and corresponding key building blocks are deeply discussed. A 1.9 GHz frequency synthesizer with a 100 kHz bandwidth is implemented with the proposed way. SpectreVerilog simulation results show that the technique can reduce over 10 dBc/Hz spurious tones. So it is suitable for high spectral purity frequency synthesizer.     

基于DDS内插PLL的设计分析

对目前常用的几种频率合成方式进行了简单介绍,阐述了直接频率合成、间接锁相环合成(PLL)以及DDS与PLL相结合的多种频率合成方式的优缺点,并着重讨论了DDS内插PLL的频率合成方法。详细阐述和分析了DDS内插PLL频率合成方式的实现方案及关键技术。针对DDS固有杂散讨论了DDS滤波器的设计并得出指导性结论。给出应用于实际电路的测试结果,证实了文中分析的正确性和实用性。     

Some Properties of Division Factor Sequences in Fractional Phase Locked Loops

In the field of fractional divider phase-locked-loops (PLL) there exist several different methods for generating the division factor sequences controlling the programmable frequency divider in the PLL. The overall behaviour of the fractional PLL strongly depends on the proper choice of the division factor sequence. Therefore some concepts for generating these fractional sequences are discussed and the behaviour of the division factor sequences will be analysed with respect to the overall PLL behaviour. In addition some sources of disturbances are mentioned.     

An Approach of Developing High Performance Millimeter-wave Frequency Synthesizer

In this paper, an approach of developing high performance millimeter-wave frequency synthesizer is proposed, which is significantly simpler than the conventional cases. The synthesizer is driven by one triple tuned typed synthesizer, which adjusts the output frequency of DDS and frequency division ratios of variable frequency divider to suppress the spurious level. With the proposed method, a microwave phase locked loop (PLL) PE3236 and a millimeter-wave multiplier HMC283 are also used. Moreover, the PLL is implemented with the form of charge pump followed by a passive three-order low-pass filter which can further suppress the phase noise. Finally, a low spurious level and high frequency resolution millimeter-wave frequency synthesizer without degradation of frequency switching speed is developed. Experimental results show that this method can achieve the performances of low spurious level, low phase noise, and high frequency resolution.     

A fully integrated V-band PLL MMIC using 0.15-/spl mu/m GaAs pHEMT technology

A fully integrated V-band phase-locked loop (PLL) MMIC with good phase noise and low-power consumption is developed using 0.15-/spl mu/m GaAs pHEMTs. For V-band frequency division,a wideband divide-by-3 frequency divider is proposed using cascode FET-based harmonic injection locking. The fourth subharmonic mixer using anti-parallel diode pair is employed as a high-frequency phase detector. In this way, the required frequency of the reference oscillator is lowered to one twelfth of V-band output signal. An RC low-pass filter and DC amplifier are also integrated to effectively suppress the spurious and harmonic signals, and to increase the loop gain. To reduce the circuit interactions and frequency pulling effect, buffer amplifiers are used at the output of VCO and frequency divider. The fabricated V-band PLL MMIC shows the locking range of 840 MHz around 60.1GHz under a very low power dissipation of 370 mW. Good phase noise of -95.5 dBc/Hz is measured at 100 kHz offset. The chip size is as small as 2.35/spl times/1.80 mm/sup 2/. To the best of our knowledge, the PLL MMIC of this work is one of the highest frequency monolithic PLLs that integrates all the required elements on a single chip.     

Analysis and minimization of substrate spurs in fractional-N frequency synthesizers

This paper analyses substrate-related spurious tones in fractional-N phase-locked loops with integrated VCOs. Spur positions are calculated and experimentally verified as a function of the divider ratios of prescaler and programmable divider. For an integrated wideband PLL in SiGe BiCMOS technology the spur power levels are measured and compared with theoretical expectations. The power in these spurs is minimized by layout techniques shielding the reference input buffer. Spur minimization by using a variable reference frequency is experimentally demonstrated. Based on this observation, a programmable integer-N PLL for driving the fractional-N synthesizer is suggested to reduce the worst-case spur level significantly.     

A low-voltage low-power programmable fractional PLL in 0.18-μm CMOS process

The prolific growth of portable electronic devices (PED) has generated tremendous interests among researchers to develop programmable phase-locked loops (PLLs) because of their abilities to produce multiple spectrally pure output frequencies from a fixed frequency oscillator. The power consumption of the RF block of a PED is mostly dominated by the programmable PLLs which are widely used in the design of these devices. Therefore to reduce the overall power consumption in a portable device and to increase the battery life time, low-voltage and low-power are the two key requirements for the PLL design. In this work an improved programmable fractional frequency divider has been incorporated to enhance the overall performance of the PLL that includes lower operating supply voltage and lower power consumption compared to the state-of-art. The proposed programmable fractional PLL has an operating frequency in the range of 1.7–2.5 GHz, and a frequency resolution of 2.5 MHz. Measurement results reveal that the proposed programmable PLL can operate at 2.4 GHz with a 1.46 V power supply voltage and only 10 mW of power consumption.     

Spurious Tone Suppression Techniques Applied to a Wide-Bandwidth 2.4 GHz Fractional-N PLL

This paper demonstrates that spurious tones in the output of a fractional-N PLL can be reduced by replacing the $DeltaSigma$ modulator with a new type of digital quantizer and adding a charge pump offset combined with a sampled loop filter. It describes the underlying mechanisms of the spurious tones, proposes techniques that mitigate the effects of the mechanisms, and presents a phase noise cancelling 2.4 GHz ISM-band CMOS PLL that demonstrates the techniques. The PLL has a 975 kHz loop bandwidth and a 12 MHz reference. Its phase noise has a worst-case reference spur power of $-$ 70 dBc and a worst-case in-band fractional spur power of $-$64 dBc.      

A 21-GHz 8-Modulus Prescaler and a 20-GHz Phase-Locked Loop Fabricated in 130-nm CMOS

A 1.5-V 256-263 8-modulus prescaler and a 1.5-V integer-N phase-locked loop (PLL) with eight different output frequencies have been implemented in a 0.13-mum foundry CMOS process. The synchronous divide-by-4/5 circuit uses current mode logic (CML) D-flip-flops with resistive loads to achieve 21-GHz maximum operating frequency at input power of 0 dBm. The divider is used to implement an 8-modulus prescaler consuming 6-mA current and 9-mW power. This extremely low power consumption is achieved by radically decreasing the sizes of transistors in the divider. Utilizing the prescaler, a charge-pump integer-N PLL has been demonstrated with 20-GHz output frequency. The in-band phase noise of the PLL at 60-kHz offset and out-of-band phase noise at 10-MHz offset are ~-80 dBc/Hz and -116.1 dBc/Hz, respectively. The locking range is from 20.05 to 21 GHz. The PLL consumes 15-mA current and 22.5-mW power from a 1.5-V power supply.     

A 2.4-GHz ring-oscillator-based CMOS frequency synthesizer with a fractional divider dual-PLL architecture

A 2.4-GHz frequency synthesizer was designed that uses a fractional divider to drive a dual-phase-locked-loop (PLL) structure, with both PLLs using only on-chip ring oscillators. The first-stage narrow-band PLL acts as a spur filter while the second-stage wide-band PLL suppresses VCO phase noise so that simultaneous suppression of phase noise and spur is achieved. A new low-power, low-noise, low-frequency ring oscillator is designed for this narrow-band PLL. The chip was designed in 0.35-/spl mu/m CMOS technology and achieves a phase noise of -97 dBc/Hz at 1-MHz offset and spurs of -55 dBc. The chip's output frequency varies from 2.4 to 2.5 GHz; the chip consumes 15 mA from a 3.3-V supply and occupies 3.7 mm/spl deg/.