一种高共模抑制比恒定跨导运算放大器

介绍了一种基于电平位移技术实现恒定跨导的CMOS Rail-to-Rail运算放大器。该电路克服了一般运算放大器输入共模范围小的特点,输入级引入了电平位移电路,使运放在各种输入共模电压下的跨导几乎恒定。在此基础上,设计了一种具有高共模抑制比的恒定跨导运算放大器。该运算放大器具有Rail-to-Rail的输入、输出能力。整个电路采用Hynix 0.5μm CMOS工艺进行设计。     

在系统可编程模拟器件简介

在分析可编程模拟器件发展的基础上，介绍了在系统可编程模拟器件ispPAC的结构、编程模块电路、编程方法、应用举例和使用的局限性。     

数字式可编程有源R方波发生器

本文指出了一种新型的数字式可编程有源R方波发生器,该电路只用了两个通用运算放大器、两个跨导型运算放大器和一些电阻。同时也作了实验,验证了理论的正确性。     

一种多功能压控振荡电路

跨导运算放大器(operational transconductance amplifier,简称OTA),常用图1的符号表示。OTA除具有常规运算放大器的同相、反相输入端外,还多了一个电信号控制端,即偏置电流输入端。将经过编程的数字或模拟信号加到这个控制端,就可以实现增益g_m的编程,因此,OTA也称为可编程运算放大器。它的特性可由如下     

一种新颖的OTA结构的数模转换器

介绍了一种新颖结构的数模转换器，此转换器的设计核心是采用跨导运算技术，由CMOS运算跨导放大器（OTA）构成。此D／A转换器以模拟电流作为主要信号变量，以跨导运算放大器取代电压运算放大器，以基于OTA的有源元件取代部分无源元件，通过改变OTA的偏置电流，从而改变其互导增益gm和电压放大器增益Au，更适合于IC的集成。采用9个OTA构成一个8位的加法电路，8个OTA的互导增益gm对应8位的数字信号，8个MOS管作为开关运用由8位的数字信号控制，从而实现数字信号到模拟信号的转换。     

基于可编程跨导运算放大器POTA低通有源滤波器设计

该文给出了基于可编程跨导运算放大器(POTA)的有源滤波器设计方法,能在一定范围内实现跨导值程控调节, 提高调节精度和准确度。并且利用Jacobi法求解相似对角形矩阵,避免解高次方程的难题。所设计的有源滤波电路不易受分布电容的影响,稳定性好、灵敏度低。本文给出了设计实例,显示了该方法的优点。     

用PAC-Designer设计滤波器

近年来,数字系统的EDA技术及可编程逻辑器件的发展极大地改变了传统电子系统的设计思想和实现方法,但是模拟电路的设计手段似乎还停滞不前。现在,由美国Lattice公司推出的模拟电路在系统可编程技术ispPAC使这种情况发生了变化,为模拟电路的设计自动化翻开了新的一页。ispPAC及PAC-Designer的特点 与数字系统的在系统可编程技术类似,模拟电路的在系统可编程技术允许设计者使用开发软件在计算机中设计和修改模拟电路,并通过编程电缆将设计方案下载到可编程模拟器件中,从而加快设计进程,提高系统设计的准确性,为电子系统设计人员开发产品提供了一条崭新的途径。目前由     

用于Sigma-Delta调制器的低电压跨导运算放大器

跨导运算放大器是模拟电路中的重要模块,其性能往往会决定整个系统的效果.这里设计了一种适用于高阶单环Sigma-Delta调制器的全差分折叠式共源共栅跨导运算放大器.该跨导运算放大器采用经典的折叠式共源共栅结构,带有一个开关电容共模反馈电路.运算放大器使用SIMC 0.18 μm CMOS混合信号工艺设计,使用Spectre对电路进行整体仿真,仿真结果表明,负载电容为5 pF时,该电路直流增益可达72 dB、单位增益带宽91.25 MHz、相位裕度83.35°、压摆率35.1 V/μs、功耗仅为1.41 mW.本设计采用1.8 V低电源电压供电,通过对电路参数的优化设计,使得电路在低电压条件下仍取得良好的性能,能满足Sigma Delta调制器高精度的要求.     

构成单片正弦波振荡器的可编程模拟电路

可编程逻辑器件为数字设计中复杂功能的实现提供了一种流行的方法。虽然制造商尚未提供能与VLSI数字电路复杂性相比拟的模拟电路,但现场可编程模拟电路正在信号调整和滤波应用中获得广泛采用。这些器件基于CMOS跨导及开关式电容放大器,可为相对复杂的设计问题提供一种便利的解决方案。Lattice     

在系统可编程模拟器件ispPAC80及其应用

介绍了在系统可编程模拟器件ispPAC80的主要结构和性能特点，以及用开发软件PAC-Designer实现各种类型5阶低通滤波器电中的方法。该电路仅需一块ispPAC80器件，而无需使用传统的运算放大器，也不需外接电阻、电容等元器件。该方法简单、快捷，修改方便。     

A field programmable analog array for CMOS continuous-time OTA-Cfilter applications

A programmable high-frequency operational transconductance amplifier (OTA) is proposed and analyzed. A general configurable analog block (CAB) is presented, which consists of the proposed programmable OTA, programmable capacitor and MOSFET switches. Using the CABs, the universal tunable and field programmable analog array (FPAA) can be constructed, which can realize many signal-processing functions, including filters. A tuning circuit is also discussed. The proposed OTA has been simulated and fabricated in CMOS technology. The results show that the OTA has the transconductance tunable/programmable in a wide range of 700 times and the -3-dB bandwidth larger than 20 MHz. A universal 5×8 CAB array has been fabricated. The chip has also been configured to realize OTA-C 60-kHz and 500-kHz bandpass filters based on ladder simulation and biquad cascade     

基于运放和模拟开关的可编程放大器实验设计

可编程放大器是电子测量常用器件,可扩大输入信号的量程范围。单片可编程放大芯片集成度高、价格不菲,学生对其内部结构了解甚少。实验采用通用运放和模拟开关实现4级量程可编程放大。学生通过实验可更好地理解可编程放大器工作原理,有益于提高学生工程实践创新能力,拓展了实验教学的深度与广度。实验电路成本低、工作稳定,可作为应急方案用于大学生电子设计竞赛等场景。     

OTRA,its implementations and applications: a state-of-the-art review

During the last three decades, a large number of new analog circuit building blocks have emerged beyond the well-known operational amplifier, operational transconductance amplifier, Current Conveyors and Current feedback operational amplifier. Among the new building blocks, the operational transresistance amplifier (OTRA) has received considerable attention in the literature. This paper presents a state-of-the-art review of the OTRAs, their bipolar and CMOS implementations and applications in linear and nonlinear analog signal processing/generation along with a comprehensive list of references covering the period from 1992 till date.     

A Novel Tunable Transconductance Amplifier Based on Voltage-Controlled Resistance by MOS Transistors

A new tunable transconductance amplifier is proposed for the programmable analog signal processing or low power filter applications. The transconductor linearization is based on the compensation of nonlinear behaviour by two MOS transistors. The transconductance amplifier in this brief exhibits the good common-mode dynamic range and the voltage-controlled transconductance. HSPICE circuit simulation using 0.18-$muhbox m$standard CMOS technology shows the$pm$50% tunable transconductance range with the$pm$0.2-V control voltage, and the linearity of less than 60 dB in the total harmonic distortion for the 0.6$hbox V_ PP$input signal.     

Current follower based reconfigurable integrator/differentiator circuits with passive and active components׳ reuse

Reconfigurable integrator/differentiator circuits based on the current follower are presented. They are essential for realizing configurable analog blocks (CABs) for field programmable analog arrays (FPAAs). The proposed circuits provide functional reconfigurations and components reuse. These functions provide flexibility in the area of filter design within CAB architectures. Circuits based on current follower have the potential to operate at higher frequency ranges and offer improved linearity over their counterparts based on the operational amplifier and transconductance amplifier, respectively. No switches are used in a signal path in order to avoid degrading the frequency response of the proposed circuits. A CMOS current follower realization compatible with implementation of the proposed designs is adopted. Experimental results obtained from a standard 0.35 µm CMOS process are provided.     

用ispPAC20和isp1032实现可编程逐次逼近式A/D转换器的研究

ispPAC20在系统可编程模拟器件集放大器、比较器、D／A转换器为一体、方便地完成放大器、有源滤波器、方波发生器等模拟电路单元的设计。还可将其与isp1032结合实现可编程的逐次逼近式A／D转换。本文给出了一个设计,它具有控制灵活,可8方便地嵌入到电子系统设计中的优点。     

A very high-frequency CMOS complementary folded cascode amplifier

A wide-band, fast settling CMOS complementary folded cascode (CFC) transconductance amplifier for use in analog VLSI high frequency signal processing applications is introduced. The superior performance of the CFC architecture over that of the folder cascode (FC) or mirrored cascode (MC) approaches for VLSI amplifiers is demonstrated. The symmetrically configured complementary input stage provides a wide common-mode input voltage range. The amplifier performs as an operational transconductance amplifier (OTA) and displays a first-order dominant pole when loaded by a shunt capacitor. The transconductance amplifier is small in area (0.016 mm²), and well suited for high frequency analog signal processing applications. Simulation and experimental results demonstrate a DC gain of approximately 50 dB, with a 0.1% settling response of under 10 ns for loads varied from 0 to 2 pF     

Two digitally programmable gain amplifiers based on current conveyors

Two digitally programmable gain amplifiers based on current conveyors (CCIIs) are presented. The first digitally programmable gain amplifier consists of a CCII, an operational transconductance amplifier (OTA), and current mirrors. The second one is composed of current conveyor analogue switches (CCASs). Both proposed digitally programmable gain amplifiers do not need switches but they maintain the linear gain at any digital signal levels similar to the digitally programmable gain amplifier using switches; hence the proposed amplifiers are easier to realize, use narrower chip area, and consume lower power. The first proposed amplifier is verified by constructing the circuit using the CCII in an AD844 IC, the OTA in a CA3080 IC, and some bipolar current mirrors. The second proposed amplifier is verified by simulating the circuit using the parameters extracted from the layout (including parasitic capacitance) in the 0.25 μm MOS technology, the level 49 MOS model obtained through MOSIS is used. The results show that the operations of two proposed amplifiers are in accordance with the theories.     

Instrumentation amplifier and current injection circuit design for input impedance boosting in biopotential and bioimpedance measurements

This paper describes an instrumentation amplifier (IA) architecture with a mechanism that generates negative capacitances at its input. Two 8-bit programmable capacitors between the input stage and the current feedback loop of the IA allow adaptive cancellation of the input capacitances from the electrode cables and printed circuit board. The proposed negative capacitance generation technique can improve the input impedance from a few megaohms to above 500 MΩ without significant impact on performance parameters such as the common-mode rejection ratio, power supply rejection ratio, total harmonic distortion, and noise. Furthermore, a current injection circuit is introduced for on-chip input impedance estimation. An operational transconductance amplifier and associated key design concepts are presented in this paper that achieve a transconductance of 25 pS and an output impedance above 4 GΩ. The IA and the test current generator were designed and simulated using 0.13 µm CMOS technology.