Breakdown voltage and current collapse of F-plasma treated AIGaN/GaN HEMTs

The breakdown and the current collapse characteristics of high electron mobility transistors （HEMTs） with a low power F-plasma treatment process are investigated. With the increase of F-plasma treatment time, the saturation current decreases, and the threshold voltage shifts to the positive slightly. Through analysis of the Schottky characteristics of the devices with different F-plasma treatment times, it was found that an optimal F-plasma treatment time of 120 s obviously reduced the gate reverse leakage current and improved the breakdown voltage of the devices, but longer F-plasma treatment time than 120 s did not reduce gate reverse leakage current due to plasma damage. The current collapse characteristics of the HEMTs with F-plasma treatment were evaluated by dual pulse measurement at different bias voltages and no obvious deterioration of current collapse were found after low power F-plasma treatment.     

Analysis of AIGaN/GaN high electron mobility transistors failure mechanism under semi-on DC stress

Semi-on DC stress experiments were conducted on A1GaN/GaN high electron mobility transistors （HEMTs） to find the degradation mechanisms during stress. A positive shift in threshold voltage （VT） and an increase in drain series resistance （RD） were observed after semi-on DC stress on the tested HEMTs. It was found that there exists a close correlation between the degree of drain current degradation and the variation in VT and RD. Our analysis shows that the variation in Vx is the main factor leading to the degradation of saturation drain current （IDs）, while the increase in RD results in the initial degradation of Ios in linear region in the initial several hours stress time and then the degradation of VT plays more important role. Based on brief analysis, the electron trapping effect induced by gate leakage and the hot electron effect are ascribed to the degradation of drain current during semi-on DC stress. We suggest that electrons in the gate current captured by the traps in the A1GaN layer under the gate metal result in the positive shift in VT and the trapping effect in the gate-drain access region induced by the hot electron effect accounts for the increase in RD.     

DC and RF characteristics of enhancement-mode InAIN/GaN HEMT with fluorine treatment

We report an enhancement-mode InA1N/GaN HEMT using a fluorine plasma treatment. The threshold voltage was measured to be ＋0.86 V by linear extrapolation from the transfer characteristics. The transconductance is 0 mS/mm at Vc, s = 0 V and VDS = 5 V, which shows a truly normal-offstate. The gate leakage current density of the enhancement-mode device shows two orders of magnitude lower than that of the depletion-mode device. The transfer characteristics of the E-mode InA1N/GaN HEMT at room temperature and high temperature are reported. The current gain cut-off frequency （fT） and the maximum oscillation frequency （fmax） of the enhancement-mode device with a gate length of 0.3 #m were 29.4 GHz and 37.6 GHz respectively, which is comparable with the depletion-mode device. A classical 16 elements small-signal model was deduced to describe the parasitic and the intrinsic parameters of the device.     

Low ohmic contact AIN/GaN HEMTs grown by MOCVD

AlN/GaN high-electron-mobility transistors （HEMTs） on SiC substrates were fabricated by metalorganic chemical vapor deposition （MOCVD） and then characterized. An Si/Ti/Al/Ni/Au stack was used to reduce ohmic contact resistance （0.33 g2.mm） at a low annealing temperature. The fabricated devices exhibited a maximum drain current density of 1.07 A/mm （Vows = I V） and a maximum peak extrinsic transconductance of 340 mS/mm. The off-state breakdown voltage of the device was 64 V with a gate-drain distance of 1.9 μm. The current gain extrinsic cutoff frequency fT and the maximum oscillation frequency fmax were 36 and 80 GHz with a 0.25 μm gate length, respectively.     

Effects of rapid thermal annealing on ohmic contact of AIGaN/GaN HEMTs

Ohmic contacts with Ti/Al/Ti/Au source and drain electrodes on A1GaN/GaN high electron mobility transistors （HEMTs） were fabricated and subjected to rapid thermal annealing （RTA） in flowing N2. The wafer was divided into 5 parts and three of them were annealed for 30 s at 700, 750, and 800 ℃, respectively, the others were annealed at 750 ℃ for 25 and 40 s. Due to the RTA, a change from Schottky contact to Ohmic contact has been obtained between the electrode layer and the A1GaN/GaN heterojunction layer. We have achieved a low specific contact resistance of 7.41 × 10-6Ω cm2 and contact resistance of 0.54 Ω.mm measured by transmission line mode （TLM）, and good surface morphology and edge acuity are also desirable by annealing at 750 ℃ for 30 s. The experiments also indicate that the performance of ohmic contact is first improved, then it reaches a peak, finally degrading with annealing temperature or annealing time rising.     

用于U波段移动数字电视的宽带大动态范围高线性度射频前端

A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced,and includes a noise-cancelling low-noise amplifier(LNA),an RF programmable gain amplifier(RFPGA) and a current communicating passive mixer.The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA.An RFPGA with five stages provides large dynamic range and fine gain resolution.A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor,and optimum linearity and symmetrical mixing is obtained at the same time.The RF front-end is implemented in a 0.25 μm CMOS process.Tests show that it achieves an ⅡP3(third-order intercept point) of –17 dBm,a conversion gain of 39 dB,and a noise figure of 5.8 dB.The RFPGA achieves a dynamic range of –36.2 to 23.5 dB with a resolution of 0.32 dB.     

Ranking Potential Reply-Providers in Community Question Answering System

Community Question Answering （CQA） websites have greatly facilitated users＇ lives, with an increasing number of people seeking help and exchanging ideas on the Internet. This newlymerged community features two characteristics： social relations and an ask-reply mechanism. As users＇ behaviours and social statuses play a more important role in CQA services than traditional answer retrieving websites, researchers＇ concerns have shifted from the need to passively find existing answers to actively seeking potential reply providers that may give answers in the near future. We analyse datasets derived from an online CQA system named ＂Quora＂, and observed that compared with traditional question answering services, users tend to contribute replies rather than questions for help in the CQA system. Inspired by the findings, we seek ways to evaluate the users＇ ability to offer prompt and reliable help, taking into account activity, authority and social reputation char- acteristics. We propose a hybrid method that is based on a Question-User network and social network using optimised PageRank algorithm. Experimental results show the efficiency of the proposed method for ranking potential answer-providers.     

一个全差分可编程的多通道神经信号记录芯片

A multi-channel,fully differential programmable chip for neural recording application is presented.The integrated circuit incorporates eight neural recording amplifiers with tunable bandwidth and gain,eight 4thorder Bessel switch capacitor filters,an 8-to-1 analog time-division multiplexer,a fully differential successive approximation register analog-to-digital converter(SAR ADC),and a serial peripheral interface for communication.The neural recording amplifier presents a programmable gain from 53 dB to 68 dB,a tunable low cut-off frequency from 0.1 Hz to 300 Hz,and 3.77 μVrms input-referred noise over a 5 kHz bandwidth.The SAR ADC digitizes signals at maximum sampling rate of 20 kS/s per channel and achieves an ENOB of 7.4.The integrated circuit is designed and fabricated in 0.18-μm CMOS mix-signal process.We successfully performed a multi-channel in-vivo recording experiment from a rat cortex using the neural recording chip.     

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.     

Low power high gain gain-controlled LNA and mixer for GNSS receivers Wei Binbin(魏斌斌)1, Jiang Jinguang(江金光)1,2,3*

A low power high gain gain-controlled LNA ＋ mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load. Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNA ＋ mixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNA ＋ mixer, a previous low power LNA ＋ mixer, and the proposed LNA ＋ mixer are presented. The circuit is implemented in 0.18 #m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2 and consumes 2 mA current under 1.8 V supply.     

一种应用于GPS接收机的高线性度SiGe HBT低噪声放大器

A high linearity 1.575 GHz SiGe：HBT low noise amplifier （LNA） for global positioning system applications is described. The bipolar cascoded with an MOSFET LNA was fabricated in a commercial 0.18 μm SiGe BiCMOS process, A resistor bias feed circuit with a feedback resistor was designed for the LNA input transistor to improve its intermodulation and compression performance. The packaged chip tested on board has displayed a noise figure of 1. I 1 dB, a power gain of 18 dB, an output 1 dB compression point of ＋7.8 dBm and an input third-order intercept point of ＋1.8 dBm. The chip occupies a 500 × 560μm^2 area and consumes 3.6 mA from a 2.85 V power supply.     

一种应用于GNSS接收机的低噪声和低杂散频率综合器

A low phase noise and low spur phase locked loop （PLL） frequency synthesizer for use in global navigation satellite system （GNSS） receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector （PFD） produces four control signals, which can reach the charge pump （CP） simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is -127.65 dBc/Hz and the reference spur is -73.58 dBc.     

一种电流复用共栅低噪声放大器的低功耗433/915-MHz射频前端的设计

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier(LNA),current-reuse V –I converter,active double balanced mixer and transimpedance amplifier for short range device(SRD) applications.With the proposed current-reuse LNA,the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices.The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm2.Operating in 433 MHz band,the measurement results show the RF front-end achieves a conversion gain of 29.7 dB,a double side band noise figure of 9.7 dB,an input referenced third intercept point of –24.9 dBm with only 1.44 mA power consumption from 1.8 V supply.Compared to other reported front-ends,it has an advantage in power consumption.     

用于无采保流水线ADC的高速低功耗低失调动态比较器

A novel fully differential high speed high resolution low offset CMOS dynamic comparator has been implemented in the SMIC 0.18 μm process used for a sample-and-hold amplifier （SHA）-less pipelined analog-to-digital converters （ADC）. Based on the analysis and optimization between delay time and offset, an enhanced reset architecture with transmission gate was introduced to speed up the comparison and reset procedure. Four inputs with two cross coupled differential pairs, reconstituted bias circuit for tail current transistor and common centroid layouts make the comparator more robust against mismatch and process variations. The simulation results demonstrate that the proposed design achieves 1 mV sensitivity at 2.2 GHz sampling rate with a power consumption of 510 μW, while the mean offset voltage is equal to 10.244 mV.     

一种基于低中频接收相位选择发射结构的工作在2.4GHz面向WPAN应用的超低功耗收发机

This paper presents a 2.4 GHz CMOS transceiver for the wireless personal area network （WPAN） inte- grated in 0.18/zm CMOS technology. This transceiver adopts a low-IF receiver, a MUX based transmitter and a fast-setting fractional-N frequency synthesizer. For achieving low cost and low power consumption, an inductor- less receiver front-end, an adaptive analog baseband, a low power MUX and a current-reused phase-locked loop （PLL） have been proposed in this work. Measured results show that the receiver achieves-8 dBrn of lIP3 and 31 dB of image rejection. The transmitter delivers 0 dBm output power at a data rate of 2 Mbps. The current consumption is 7.2 mA in the receiving mode and 6.9 mA in the transmitting mode, respectively.     

用于流水线ADC的频率自适应可编程MDAC电路

A programmable high precision multiplying DAC （MDAC） is proposed. The MDAC incorporates a frequency-current converter （FCC） to adjust the power versus sampling rate and a programmable operational am- plifier （POTA） to achieve the tradeoff between resolution and power of the MDAC, which makes the MDAC suitable for a 12 bit SHA-less pipelined ADC. The prototype of the proposed pipelined ADC is implemented in an SMIC CMOS 0.18 μm 1P6M process. Experimental results demonstrate that power of the proposed ADC varies from 15.4 mW （10 MHz） to 63 mW （100 MHz） while maintaining an SNDR of 60.5 to 63 dB at all sampling rates. The differential nonlinearity and integral nonlinearity without any calibration are no more than 2.2/-1 LSB and 1.6/-1.9 LSB, respectively.     

A 130 nm CMOS low-power SAR ADC for wide-band communication systems

This paper presents a low power 9-bit 80 MS/s SAR ADC with comparator-sharing technique in 130 nm CMOS process. Compared to the conventional SAR ADC, the sampling phase is removed to reach the full efficiency of the comparator. Thus the conversion rate increases by about 20% and its sampling time is relaxed. The design does not use any static components to achieve a widely scalable conversion rate with a constant FOM. The floorplan of the capacitor network is custom-designed to suppress the gain mismatch between the two DACs. The ＇set-and- down＇ switching procedure and a novel binary-search error compensation scheme are utilized to further speed up the SA bit-cycling operation. A very fast logic controller is proposed with a delay time of only 90 ps. At 1.2 V supply and 80 MS/s the ADC achieves an SNDR of 51.4 dB and consumes 1.86 mW, resulting in an FOM of 76.6 fJ/conversion-step. The ADC core occupies an active area of only 0.089 mm2.     

一种应用于无线局域网具有3.01-3.82 GHz频率范围和6.29%调谐增益变化的CMOS LC压控振荡器

A wideband low-phase-noise LC voltage-controlled oscillator （VCO） with low VCO gain （Kvco） vari- ation for WLAN fractional-N frequency synthesizer application is proposed and designed on a 0.13-μm CMOS process. In order to achieve a low Kvco variation, an extra switched varactor array was added to the LC tank with the conventional switched capacitor array. Based on the proposed switched varactor array compensation technique, the measured Kvco is 43 MHz/V with only 6.29% variation across the entire tuning range. The proposed VCO provides a tuning range of 23.7% from 3.01 to 3.82 GHz, while consuming 9 mA of quiescent current from a 2.3 V supply. The VCO shows a low phase noise of-121.94 dBc/Hz at 1 MHz offset, from the 3.6 GHz carrier.     

纳米锥SiGe-SOI光波导与光纤的耦合分析

Based on a submicrometer-sized SiGe-SOI waveguide, the coupling loss mechanism is analyzed between the submicrometer-sized SiGe-SOI waveguide and the fiber. The main sources of coupling loss are analyzed, and the mismatch loss of the mode field is the mainly lost during connection between the submicrometer-sized waveguide and the fiber. In order to reduce the mismatch loss of the mode field, the structure ofa nanotaper SiGeSOI waveguide with a nanometer-sized tip is adopted. By reducing the waveguide dimensions to increase the mode field size, coupling loss could be reduced between the waveguide and the fiber. Different mode field dimensions ofnanotaper SiGe-SOI waveguides and fiber are quantitatively analyzed, and the quantitative relationship between nanotaper SiGe-SOI waveguide dimensions and mode field dimensions are obtained. Finally, nanotaper SiGe-SOI waveguides are made, and the test and analysis have been done. The final experimental results accord well with the theoretical analysis. When the waveguide width is 0.5 μm, the minimum coupling loss of the SiGe-SOI waveguide is 0.56 dB/facet, and also the correctness of the design method and theoretical analysis are verified.