A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver

An 8-Gb/s 0.3-μm CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear phase-locked loop that achieves a loop bandwidth of 35 MHz, phase margin of 50°, and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8 Gb/s data are successfully detected by the receiver after a 10-m coaxial cable. The 2×2 mm² chip consumes 1.1 W at 8 Gb/s with a 3-V supply     

A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

This paper describes the design and implementation of a quad high-speed transceiver cell fabricated in 0.13-/spl mu/m CMOS technology. The clocking circuit of the cell employs a dual-loop architecture with a high-bandwidth core phase-locked loop (PLL) and low-bandwidth digitally controlled interpolators. To achieve low jitter while maintaining low power consumption, the dual-loop PLL uses two on-chip linear regulators of different bandwidths, one for the core and the other for the interpolator loop. The prototype chip operates from 400 Mb/s to 4 Gb/s with a bit error rate of <10/sup -14/. The quad cell consumes 390 mW at 2.5 Gb/s (95 mW/link) under typical operating conditions with a 400-mV output swing driving double terminated links.     

A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization

In this paper, a serial link design that is capable of 4.8-6.4-Gb/s binary NRZ signaling across 40' of FR4 copper backplane traces and two connectors is described. The transmitter features a programmable two-tap feed forward equalizer and the receiver uses an adaptive four-tap decision feedback equalization to compensate for the losses in the channel at 6.4 Gbps. The transceiver core is built in LSI's 0.13-/spl mu/m standard CMOS technology to be integrated into ASIC designs that require serial links. The transceiver consumes 310 mW per duplex channel at 1.2 V and 6.4 Gb/s under nominal conditions.     

A 0.5-μm CMOS 4.0-Gbit/s serial link transceiver with datarecovery using oversampling

A 4-Gbit/s serial link transceiver is fabricated in a MOSIS 0.5-μm HPCMOS process. To achieve the high data rate without speed critical logic on chip, the data are multiplexed when transmitted and immediately demultiplexed when received. This parallelism is achieved by using multiple phases tapped from a PLL using the phase spacing to determine the bit time. Using an 8:1 multiplexer yields 4 Gbits/s, with an on-chip VCO running at 500 MHz. The internal logic runs at 250 MHz. For robust data recovery, the input is sampled at 3× the bit rate and uses a digital phase-picking logic to recover the data. The digital phase picking can adjust the sample at the clock rate to allow high tracking bandwidth. With a 3.3-V supply, the chip has a measured bit error rate (BER) of <10^-14     

2.5 Gbit/s multifunctional CMOS transceiver for chip-to-chip optical link

A novel multifunctional transceiver for chip-to-chip optical interconnects operating at 2.5 Gbit/s is proposed, which shares a common block between a receiver and a transmitter. This transceiver provides four conversion functions - electrical-to-optical, optical-to-optical, optical-to-electrical, and electrical-to-electrical - depending on the selection switch on a single chip. The whole chip integrated in 0.18 /spl mu/m CMOS occupies an area measuring 0.82/spl times/0.82 mm/sup 2/.     

An adaptive PAM-4 5-Gb/s backplane transceiver in 0.25-/spl mu/m CMOS

This paper describes a backplane transceiver, which uses pulse amplitude modulated four-level (PAM-4) signaling and continuously adaptive transmit-based equalization to move 2.5-GBd/s symbols totalling 5 Gb/s across typical FR-4 backplanes for total distances of up to 50 inches through two sets of backplane connectors. The 17-mm/sup 2/ device is implemented in a 0.25-/spl mu/m CMOS process, operates off of 2.5- and 3.3-V supply voltages, and consumes 1 W.     

A 2.5-3.125-Gb/s quad transceiver with second-order analog DLL-based CDRs

This paper describes a 2.5-3.125-Gb/s quad transceiver with second-order analog delay-locked loop (DLL)-based clock and data recovery (CDR) circuits. A phase-locked loop (PLL) is shared between receive (RX) and transmit (TX) chains. On each RX channel, an amplifier with user-programmable input equalization precedes the CDR. Retimed data then goes to an 1:8/1:10 deserializer. On the TX side, parallel data is serialized into a high-speed bitstream with an 8:1/10:1 multiplexer. The serial data is introduced off-chip through a high-speed CML buffer having single-tap pre-emphasis. Proposed DLL-based CDR can tolerate large frequency offsets with no jitter tolerance degradation due to its second-order PLL-like nature. Also, this study introduces an improved charge-pump and an improved phase-interpolator. Fabricated in a 0.15-/spl mu/m CMOS process, the 1.9-mm/sup 2/ transceiver front-end operates from a single 1.2-V supply and consumes 65-mW/channel of which 32 mW is due to the CDR. CDR jitter generation and high-frequency jitter tolerance are 5.9 ps-rms and 0.5 UI, respectively, for 3.125 Gb/s, 2/sup 23/-1 PRBS input data with 800-ppm frequency offset.     

A CMOS multichannel 10-Gb/s transceiver

We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification.     

A CMOS 400-Mb/s serial link for AS-memory systems using a PWMscheme

In this paper, a serial link for AS-memory systems fabricated in a 0.25-μm standard CMOS technology is presented. This serial link utilizes a pulsewidth modulation (PWM) technique. By transmitting the PWM-encoded signal with periodic rising edges, the clock can be implicitly embedded in the data stream and the associating overhead needed in clock/data recovery circuits can, be mitigated. The symbol rate is 200 Mb/s and the equivalent data rate is 400 Mb/s. The PWM transceiver dissipates 66.5 mW at a 2.5-V supply voltage. It is suitable for the AS-memory systems in which the pin count is limited and elaborate clock/data recovery circuits are not required     

A CMOS 10-gb/s SONET transceiver

This paper presents a single-chip SONET OC-192 transceiver (transmitter and receiver) fabricated in a 90-nm mixed-signal CMOS process. The transmitter consists of a 10-GHz clock multiplier unit (CMU), 16:1 multiplexer, and 10-Gb/s output buffer. The receiver consists of a 10-Gb/s limiting input amplifier, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. Both transmit and receive phase-locked loops employ a 10-GHz on-chip LC voltage-controlled oscillator (VCO). This transceiver exceeds all SONET OC-192 specifications with ample margin. Jitter generation at 10.66-Gb/s data rate is 18 mUI/sub pp/ (unit interval, peak-to-peak) and jitter tolerance is 0.6 UI/sub pp/ at 4-MHz jitter frequency. This transceiver requires 1.2V for the core logic and 1.8 V for input/output LVDS buffers. Multiple power supply domains are implemented here to mitigate crosstalk between receiver and transmitter. The overall power dissipation of this chip is 1.65 W.     

针对10Gb/s线卡应用的灵活接口方案

许多网络应用都采用10Gb／s接口来减小通信瓶颈。例如,用户对低成本千兆以太网(GbE)接入和VPLS需求的不断高涨,推动着运营商投入巨大力量建设10GbE城域网。这些网络是对已经向10Gb／s SDH(STM-64)和DWDM(密集波分复用)发展的现有传输网络的补充。另外,这些网络所传输的内容一般缘于一个大的数据中心,而这些数据中心都是考虑用通过10Gb／s光纤通道接口连接到光通道交换机,进而和服务器联系在一起,并依次连接交换机和存储子系统。     

Differential current mode serial link for 2 Gb/s in GaAs technology

Today's data communication systems are demanding increasing off-chip data rates. To satisfy this demand, high-speed serial links are used, saving area and power dissipation compared to highly parallel buses. However, power dissipation and noise generated by this system is still a critical issue. In this article, a novel approach using differential current mode is presented, which combines low power dissipation with low noise generated due to the reduced power transmission.     

2.5Gb/Scmos光接收机跨阻前置放大器

给出了一种利用0.35μm CMOS工艺实现的2.5Gb/s跨阻前置放大器。此跨阻放大器的增益为59 dB*Ω,3dB带宽为2GHz,2GHz处的等效输入电流噪声为0.8×10-22 A2/Hz。在标准的5V电源电压下,功耗为250mW。PCML单端输出信号电压摆幅为200mVp-p。整个芯片面积为1.0mm×1.1mm。     

2.5Gb/s和3.125Gb/s速率级0.35μmCMOS限幅放大器

采用了TSMC0.35μm CMOS工艺实现了可用于SONET/SDH2.5Gb/s和3.125Gb/s速率级光纤通信系统的限幅放大器。通过在芯片测试其最小输入动态范围可达8mVp—p，单端输出摆幅为400mVp-p，功耗250mW，含信号丢失检测功能，可以满足商用化光纤通信系统的使用标准。     

Design, modeling, and hardware correlation of a 3.2Gb/s/pair memory channel

With the rapid advance of silicon process technology, it is now possible to design input/output (I/O) circuits that operate at multigigabit data rates. As a result, accurate modeling and analysis of high-speed interconnect systems is essential to optimize the performance of the overall system. This paper describes the interconnect design, modeling, simulation, and characterization methodologies that are essential to achieve multigigabit data rates. It focuses on the physical layer verification and hardware correlation of functional systems and silicon to ensure robust system operation over 3.2Gb/s data rate using conventional low-cost packaging and printed circuit board (PCB) technologies. In order to capture conductor and dielectric losses, as well as other high-frequency effects of three-dimensional structures, accurate measurement-based simulation techniques that directly incorporate frequency-domain parameters from measurement or electromagnetic solver parameters into circuit simulation tools using fast Fourier transform (FFT) and bandlimiting windowing techniques are developed. Finally, simulation waveforms are correlated with prototypes at both component and system levels in both time and frequency domains.     

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm².     

A CMOS 1 Gb/s 5-Tap Fractionally-Spaced Equalizer

This paper presents the design of a 1 Gb/s 5-tap T/2 fractionally-spaced equalizer. The T/2 delay lines are based on third-order linear-phase double terminated sections that offer a tunable group delay of 500 ps with less than 10% ripple and a 3 dB bandwidth greater than 600 MHz. Furthermore, the equalizer architecture introduces a broadband summing circuit using a transimpedance $I/V$ converter that increases the bandwidth by a factor of 3.6 over a conventional resistive loaded analog adder. The topology's performance is demonstrated in the equalization of 1 Gb/s binary data through CAT5e twisted-pair cables for up to 23 meters. The vertical eye-opening increases from 0% to 58%. Implemented in CMOS 0.35 $mu{hbox{m}}$, the transversal equalizer occupies an area of 26 ${hbox{mm}}^{2}$ and consumes 32 mA.      

A CMOS serial link for fully duplexed data communication

This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 μm CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns