基于遗传算法的网络处理器异构资源映射方法研究

随着深亚微米工艺的迅速发展,现代网络处理器芯片广泛采用MPSoC(Multi-Processor System on Chip)体系结构实现,继而需要一种新的设计方法指导网络处理器体系结构设计.本文研究了网络处理器的设计方法,提出了一种基于遗传算法的网络应用到网络处理器异构硬件资源映射方法.该方法首先对网络处理器设计的问题空间进行分析,采用加权数据流进程网络描述网络应用,并参数化各种硬件资源,最后构建遗传算法来完成网络应用到异构硬件资源的映射,形成网络处理器体系结构设计方案.     

Hurst指数估计法中的修正方法研究

Hurst参数是表征网络业务量自相似性的重要参数,对突发业务的Hurst参数进行准确的估计能直接影响网络流量控制和缓冲资源分配。详细给出4种Hurst参数估计方法的实现过程,并针对这4种估计方法进行修正。通过估计不同Hurst参数的自相似业务量来对比修正前后估计方法的精度,结果表明采用修正的方法各个估计方法的相对误差都有降低,其中R/S法降低了2个百分点,聚类方差法降低了8个百分点,周期图法和小波分析法相对误差降低了一个数量级。     

访存敏感的增量式MPSoC应用映射

现代多处理器片上系统(multiprocessor system-on-chip,MPSoC)通常采用片上网络(network-on-chip,NoC)作为其基本互连结构,应用映射是基于片上网络互连的MPSoC设计中的关键问题,应用映射决定应用划分成的各个任务到片上网络节点的分配.许多基于片上网络互连的MPSoC系统将共享存储作为网络中的独立节点,针对这类MPSoC系统,提出一种访存敏感的增量式动态映射策略.该策略离线分析获取应用的访存特征,运行中当应用到达系统时,根据其访存特征选择不同的映射算法,将热点应用围绕共享存储器布局,非热点应用远离共享存储器布局,并最小化应用间以及应用所含任务间的通信链路竞争.模拟实验表明:与贪恋区域选择加随机节点映射的策略相比较,提出的策略对系统整体通信功耗平均节约34.6％,性能提升可达36.3％,并能适应不同片上网络规模.     

基于PSoC的瞳孔光刺激与测量系统

瞳孔跟随光刺激的变换检测系统可广泛用于疲劳检测、颅内损伤检测等方面。为实现方便可控的刺激光源生成和光强检测,设计实现基于PSoC（Programmable System on Chip,片上可编程系统）芯片的光刺激与测量系统。以PWM（脉冲宽度调制）的方式驱动LED,PC端设计了应用控制界面,可以调节LED光照刺激的强度频率等参数,并实时获得光强数据。系统实际运用于实时瞳孔参数检测平台,提供稳定可控的光刺激与测量功能。     

异构多处理器SoC 的应用算法性能优化方法

在嵌入式多媒体处理领域中,多处理器片上系统(multi-processor system-on-chip,简称MPSoC)的应用越来越广泛.多媒体处理MPSoC通常采用"主处理器核+多个异构协处理器核"的主流体系结构.该结构兼顾了MPSoC系统的通用性与灵活性、性能与功耗,但也向MPSoC的性能优化方法提出了更高的要求.针对异构MPSoC上的多媒体应用算法,提出了一种MPSoC多媒体处理性能优化方法.该方法经过应用特征分析、循环仿射划分、应用向MPSoC各处理器核的映射,实现了优化的数据局部性与多级并行性,从而提高了异构MPSoC上多媒体应用算法的性能.实验结果表明,该方法对于多媒体应用算法在异构MPSoC上的处理性能优化方面取得了明显效果.     

片上通信结构——共享总线和NoC的分析与比较

采用模块化方法对集中式仲裁共享总线和二维网格片上网络(Network on Chip,NoC)的硬件开销和延迟进行了数学上的分析。在此基础上,通过可综合Verilog代码对这两种片上通信结构在RTL级进行描述,并建立了这两种通信方式的周期准确级的功能验证和性能分析环境。结果表明,在同样工艺条件下,共享总线的面积与NoC相比相当小;但对于大规模片上系统通信,NoC的吞吐效率及带宽明显优于共享总线。     

基于一种新网络拓扑结构的低功耗研究

随着芯片集成度的提高,片上网络(Network on Chip,NoC)是片上系统(System on Chip,SoC)发展的必然趋势,其中功耗成为限制性能提高的瓶颈.为了降低NoC的功耗,提出一种新的拓扑结构HMesh(Hexagon Mesh)及适用于该拓扑结构的HM路由算法,并对Mesh、Torus和HMesh结构的功耗进行了仿真实验.实验结果表明,在网络不发生拥塞时,HMesh结构的平均功耗比Mesh结构和Torus结构分别降低了12.9％和11.24％,更适合片上网络的构造.     

不规则IP模块到2维NoC结构的映射方法研究

提出了一种新的基于NoC(Network on Chip)的不规则IP模块映射方法.其基本思想是把较大的IP模块分解成几个小的IP虚模型,或把几个较小的IP模块组合成一个IP虚模型,使得每个IP虚模型能映射到NoC结构的一个资源节点上.通过计算曼哈顿距离和输入/输出度,可以确定每个通信节点中缓冲区的大小.根据计算的通信代价可以对初始映射结果进行调整,从而可以避免通信拥塞,降低系统的功耗.     

视觉传感网络分布式在线数据关联

数据关联是视觉传感网络监控系统的基本问题之一. 本文针对无重叠视域视觉监控网络的多目标跟踪问题提出一种 基于多外观模型的视觉传感网络在线分布式数据关联方法,将同一目标在不同摄像机节点上的外观用不同的高斯模型描述,由分布式推理算法综合利用外观与时空观测计算关联变量的后验概率,同时通过近似最大似然估计算法对各传感节点上的外观模型参数进行在线估计. 实验结果表明了所提方法的有效性.     

基于层叠模型的网络流量异常检测方法*

进行网络流量异常检测,需要对正常流量行为建立准确的模型,根据异常流量与正常模型间的偏离程度作出判断。针对现有网络流量模型中自相似模型与多分形模型无法全面刻画流量特征的不足,提出了一种基于流量层叠模型分析的异常检测算法,采用层叠模型对整个时间尺度上的流量特征进行更准确的描述,并运用小波变换对流量的层叠模型进行估计,分析异常流量对模型估计的影响,提出统计累计偏离量进行异常流量检测的方法。仿真结果表明,该方法能够有效检测出基于自相似Hurst系数方法不能检测的弱异常以及未明显影响Hurst系数变化的异常流。     

A modeling tool for simulating and design of on-chip network systems

The conception of Network-on-Chip (NoC) presents system designers with a new approach to the design of on-chip inter-connection structures. However, such networks present designers with a large number of design parameters and decisions, many of which are critical to the efficient operation of over-all on-chip system. To aid the design process of complex systems-on-chip, this paper presents a NoC simulation environment that has been developed and implemented using the SystemC transaction-level modeling language. The simulation environment consists of on-chip components as well as traffic generators, which can generate various types of traffic patterns. The simulation environment has also been integrated with the NoC topology generation tool being developed in our group. A set of simulation results demonstrates the types of parameters that can affect the performance of on-chip systems, including topology variations, network latency and achievable throughput. These results also verify the modeling capabilities of the proposed simulation environment.     

分析网络通信量的一个新方法:PCA

分析网络通信量的传统方法是使用变尺度函数计算Hurst参数,其计算结果不准确,不能正确判断模型拟合度。文章使用主成分分析计算Hurst参数,判断通信量模型的拟合度,分析同一模型不同参数的差别不明显的数据,结果表明该方法新颖而有效。     

Buffer planning for application-specific networks-on-chip design

Networks-on-chip (NoC) is a promising communication architecture for next generation SoC. The size of buffer used in on-chip routers impacts the silicon area and power consumption of NoC dominantly. It is important to plan the total buffer-size and each router buffer-allocation carefully for an efficient NoC design. In this paper, we propose two buffer planning algorithms for application-specific NoC design. More precisely, given the traffic parameters and performance constraints of target application, the proposed algorithms automatically determine minimal buffer budget and assign the buffer depth for each input channel in different routers. The experimental results show that the proposed algorithms can significantly reduce total buffer usage and guarantee the performance requirements. Supported by the National Natural Science Foundation of China (Grant No. 60803018)     

Synthesis of dependency-aware traffic generators from NoC simulation traces

Networks-on-chip (NoCs) are currently the most appropriate communication infrastructure for many-core embedded systems. As NoCs become a de facto standard for on-chip systems, traffic generation models become critical for system-on-chip (SoC) design. Traditional trace-based traffic distorts the injection rate and the effects of congestion due to the lack of packets dependency information. They also have large data storage requirements. In this paper, we propose a new framework to process traces generated by message passing applications modeled as acyclic task graphs. This framework builds dependency-aware traffic generators (DATGs) by retrieving the packet dependencies from traces in a single simulation. The DATGs accurately replace the application nodes in emulations or simulations to explore the NoC design space. Our experimental analysis showed that our framework is more accurate than trace-based simulation for a broad range of NoC configurations. Moreover, our proposed framework uses only 3% of the data storage required by the traces.     

基于FARIMA模型的Internet网络业务预报

最近的网络研究发现Internet网络业务同时呈现长相关和短相关特性,因此建立可以同时描述,预报长相关和短相关特性的网络业务模型很有必要。文中给出了利用FARIMA模型进行建模和预报的方法,实验表明这种方法用于实际Internet网络trace是非常有效的,另外提供了简化FARIMA模型拟合的方法和具体步骤,这样大大缩短了模型辨识的时间,对于实际网络预报有很好的实用性。     

自相似参数辨识与汇聚无线业务尺度特性分析

Hurst参数是衡量网络流量自相似程度和突发性的重要参数,在时域R/S统计、方差 - 时间图法和频域周期图法的基础上,提出一种最优化线性回归小波模型,实现小波域内Hurst参数的准确有效快速辨识.研究了WLAN中多个输入业务源的汇聚过程以及汇聚的多输入自相似业务源统计特性.仿真实验比较了传统的以及基于最优化线性回归小波模型的Hurst参数辨识方法,验证了理论分析中汇聚自相似业务也呈现自相似性的结论,且仿真结果表明,汇聚业务的突发性得到加强而不是削弱.研究结论对网络流量的准确建模以及网络传输中流量控制和优化网络资源配置以及提高网络性能具有重要作用.     

A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip

Network-on-Chip (NoC) interconnect fabrics are categorized according to trade-offs among latency, throughput, speed, and silicon area, and the correctness and performance of these fabrics in Field-Programmable Gate Array (FPGA) applications are assessed through experimentation and simulation. In this paper, we propose a consistent parametric method for evaluating the FPGA performance of three common on-chip interconnect architectures namely, the Mesh, Torus and Fat-tree architectures. We also investigate how NoC architectures are affected by interconnect and routing parameters, and demonstrate their flexibility and performance through FPGA synthesis and testing of 392 different NoC configurations. In this process, we found that the Flit Data Width (FDW) and Flit Buffer Depth (FBD) parameters have the heaviest impact on FPGA resources, and that these parameters, along with the number of Virtual Channels (VCs), significantly affect reassembly buffering and routing and logic requirements at NoC endpoints. Applying our evaluation technique to a detailed and flexible cycle accurate simulation, we drive the three NoC architectures using benign (Nearest Neighbor and Uniform) and adversarial (Tornado and Random Permutation) traffic patterns with different numbers of VCs, producing a set of load–delay curves. The results show that by strategically tuning the router and interconnect parameters, the Fat-tree network produces the best utilization of FPGA resources in terms of silicon area, clock frequency, critical path delays, network cost, saturation throughput, and latency, whereas the Mesh and Torus networks showed comparatively high resource costs and poor performance under adversarial traffic patterns. From our findings it is clear that the Fat-tree network proved to be more efficient in terms of FPGA resource utilization and is compliant with the current Xilinx FPGA devices. This approach will assist engineers and architects in establishing an early decision in the choice of right interconnects and router parameters for large and complex NoCs. We demonstrate that our approach substantially improves performance under a large variety of experimentation and simulation which confirm its suitability for real systems.     

Evaluation of energy and buffer aware application mapping for networks-on-chip

Networks-on-Chip (NoC) is a communication paradigm for Systems-on-Chip (SoC). NoC design flow contains many problems, one of which is called as application mapping problem, which is generally solved in the literature by considering minimization of the communication energy consumption only. Energy and Buffer Aware Application Mapping (EBAM) is a recently proposed method, which handles the application mapping issue as a joint optimization problem for minimizing the energy consumption and buffer utilization simultaneously. EBAM avoids possible high input loads on router buffers at the early mapping stage by using a priori traffic characteristics of the application. Self similarity is already an accepted model in local and wide area networks and many on-chip applications have also been proven to have self similar characteristics. EBAM therefore employs self similar traffic in its joint optimization process and a genetic algorithm is already proposed for its solution.     

A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure

As System-on-Chips (SoCs) grow in complexity and size, proposals of networks-on-chip (NoCs) as the on-chip communication infrastructure are justified by reusability, scalability, and energy efficiency provided by the interconnection networks. Simulation and mathematical analysis offer flexibility for the evaluations under various network configurations. However, the accuracy of such analyzing methods largely depends on the approximations made. On the other hand, prototyping can be used to improve the evaluation accuracy by bringing the design closer to reality. In this paper, we propose a FPGA prototype that is general enough to model different video-processing SoCs where different cores communicate via NoC. To model NoC, we accurately implement a fully-synthesized on-chip router supporting multiple virtual channels. For the processing nodes, on the other side, we propose a general and simple traffic generator capable of modeling different synthetic functions (i.e. Poisson and self-similar). Indeed, the application traffic is modeled using 1-D hybrid cellular automata which can effectively generate high quality pseudorandom patterns. Finally, for the energy efficiency, the proposed prototype is capable to support multiple frequency regions. To realize the voltage–frequency island partitioned SoC, we use the utilities that Xilinx FPGA platform offers to design Globally Synchronous Locally Asynchronous (GALS) systems via Delay-Locked Loop elements.