基于MSMV的抗差分能量攻击电路设计及其应用

为有效消除密码器件在执行算法时以能量消耗方式泄漏密码信息,本文通过对灵敏放大型逻辑和差分能量攻击原理的研究,采用多电源和多阈值电压(Muti-Supply Muti-V th ,MSMV)CMOS电路技术设计一种具有低功耗和抗差分能量攻击性能的逻辑电路,实现对输出负载低摆幅充放电.依此进一步提出一种新型全加器结构,从而可以以低摆幅的方式对双轨电路进行编码.HSPICE模拟验证表明,所设计的全加器逻辑功能正确,抗差分能量攻击性能明显.与传统基于SABL逻辑的全加器比较,该结构具有显著的低功耗特性.     

基于MOBILE的JK触发器设计

介绍了一种新型量子逻辑单元电路——单稳双稳转换逻辑单元及其工作原理,在此基础上探讨并设计了以MOBILE为基本单元电路的具有同步置位复位功能的边沿型JK触发器电路,从而丰富了量子电路中触发器的类型     

基于MOBILE的JK触发器设计

介绍了一种新型量子逻辑单元电路--单稳双稳转换逻辑单元及其工作原理,在此基础上探讨并设计了以MOBILE为基本单元电路的具有同步置位复位功能的边沿型JK触发器电路,从而丰富了量子电路中触发器的类型.     

基于74LS112JK触发器的抢答器设计

根据JK触发器在每个时钟脉冲作用时间内，其状态只变化一次，而且不同引脚都可以使触发器状态发生改变的特性，给出了用JK触发器来设计抢答器的设计方法及仿真，同时给出了用74LS112JK触发器设计抢答器的最优设计方法及思路。     

基于JK触发器的12归1计数器的设计与实现

触发器是数字电路的基本逻辑单元之一，也是构成各种时序电路的最基本逻辑单元。文中给出了基于JK触发器来设计十二归一计数器的设计和实现方法，并通过EWB软件进行了仿真。     

线性反馈移位寄存器的差分能量攻击

能否有效去除算法噪声的影响,直接关系到能量攻击成败。该文以线性反馈移位寄存器(LFSR)相邻两个时钟周期的能量消耗差异为出发点,提出了一种新的差分能量攻击算法。它从根本上去除了密码算法噪声在攻击过程中带来的影响。由于该算法随机选择初始向量(initialization vector),从而使攻击者能够容易地将其推广到具有类似结构的流密码体制。为了进一步验证攻击算法的有效性,该文利用软件仿真的方法对DECIM进行了模拟攻击。仿真结果表明,该攻击算法能够有效降低LFSR的密钥搜索的复杂度。     

能量回收技术在D触发器上的应用

将能量回收技术应用于灵敏放大器型D触发器(SAERD),该电路采用单相正弦时钟,用来回收时钟端的能量,对于触发器的内部节点和存储单元仍采用恒定电源。在时钟频率为100～300MHz时,时钟端的功耗较输入方波时平均节省约80%。在SMIC0.13μm工艺下将SAERD应用于一款函数发生器,并与传统主从型D触发器(MSD)实现的电路进行功耗比较。仿真结果显示,时钟频率为200MHz时,功耗节省高达17.1%。     

基于差分传输管预充电逻辑的功耗恒定性电路改进设计

通过分析差分传输管预充电逻辑(DP2L)的电路结构,发现该电路还无法达到完全的功耗恒定特性,仍然存在被功耗攻击的风险.针对该问题,该文对DP2L的电路结构进行改进,并用Hspice对改进前后的电路进行模拟仿真测试.实验表明:改进后的DP2L电路结构具有更好的功耗恒定特性,更能满足该逻辑电路的设计要求.     

基于差分传输管预充电逻辑的功耗恒定性电路改进设计

通过分析差分传输管预充电逻辑(DP2L)的电路结构,发现该电路还无法达到完全的功耗恒定特性,仍然存在被功耗攻击的风险.针对该问题,该文对DP2L的电路结构进行改进,并用Hspice对改进前后的电路进行模拟仿真测试.实验表明:改进后的DP2L电路结构具有更好的功耗恒定特性,更能满足该逻辑电路的设计要求.     

芯片密码引擎抗能量攻击的几种设计措施

随着能量攻击技术已经日渐成熟,其对密码安全芯片威胁也越来越大,抗能量攻击设计也成为密码芯片设计不可或缺的一部分。论文介绍了密码芯片所面临的能量攻击的理论原理,并基于目前芯片密码引擎设计,提出了几种常用的抗能量攻击设计措施。     

An integrated JK flip-flop circuit

An integrated JK flip-flop circuit, which is constructed using an RS flip-flop and four gates, is described. The circuit operation is based on an original concept, which is different from the conventional master-slave principle. Results of a monolithic integration using emitter-coupled logic (ECL) circuits are also given. As compared with the conventional master-slave-type JK flip-flop, which is constructed using ECL, a 40 percent improvement in speed-power product has been obtained.     

低功耗四边沿触发器设计

根据在保持电路原有性能的前提下可通过降低时钟频率来降低系统功耗的原理和双边沿触发器的设计思想,本文将多值信号信息量大的优点应用于时钟网络上设计了基于三值时钟的四边沿触发器,消除了三值时钟的冗余跳变,从而通过降低时钟频率的方式达到降低功耗的目的。本文设计的四边沿触发器电路结构简单,既可以用于二值时序电路中也可以用于多值时序电路中。模拟结果表明,本文设计的四边沿触发器具有正确的逻辑功能且能有效地降低系统功耗。     

基于去抖动的JK触发器实验设计

JK触发器是一种功能完善且应用很广泛的触发器。在实验中,JK触发器实验虽然用Protues软件仿真能顺利完成,但是在实验箱上连接电路却不能得到预期的正确结果,这是开关抖动造成的。在此引入一种改进的电路:在时钟信号产生电路中引入由基本RS锁存器构成的去抖动电路,其可以有效地消除触点抖动造成的实验结果错误和误触发,得到与理论完全一致的结果。     

确定非正常触发主从JK触发器次态的一种简单方法

通过对非正常触发时主从JK触发器可能出现的工作波形的详细分析,归纳出了非正常触发时确定主从JK触发器次态的简单方法。     

Conditional-capture flip-flop for statistical power reduction

This paper describes a family of novel low-power flip-flops, collectively called conditional-capture flip-flops (CCFFs). They achieve statistical power reduction by eliminating redundant transitions of internal nodes. These flip-flops also have negative setup time and thus provide small data-to-output latency and attribute of soft-clock edge for overcoming clock skew-related cycle time loss. The simulation comparison indicates that the proposed differential flip-flop achieves power savings of up to 61% with no impact on latency while the single-ended structure provides the maximum power savings of around 67%, as compared to conventional flip-flops. With a typical switching activity of 0.33, the power consumption is reduced by as much as 23-30% with comparable minimum data-to-output latency. It is also indicated that the proposed single-ended structure provides power comparable to the fully static master-slave design with significantly reduced data-to-output latency. An eight-bit counter was fabricated using a 0.35-μm CMOS technology, and the experimental results indicate that the counter using the differential CCFF saves the overall power consumption by about 30% as compared to that using the conventional flip-flop     

Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead

Fine-grained power gating is the rigorous application of sleep transistor scheme to reduce stand-by power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, that preserves the logical state of the circuit during these short idle periods. This dynamic state retention flip-flop requires neither additional control signals nor an additional power supply for its state retention functionality. An integration into a standard design flow is possible without any modifications. The tradeoff between propagation delay and retention time is derived analytically. Retention times in the range of milliseconds can be achieved with D-to-Q delays of 100 ps to 200 ps.     

一种CMOS双沿触发器的设计

基于CMOS传输门，分析了单、双沿触发器的逻辑结构，分析了一种晶体管数较少的CMOS双沿触发器，并用PSPICE程序进行了模拟，结果表明这种双沿触发器具有完整的逻辑功能，且具有结构简单，延迟时间短和数据处理能力高的优点，另外，与传统的单沿触发器相比，其功耗大约减少了61%。     

Low power flip-flop with clock gating on master and slave latches

A new flip-flop is presented in which power dissipation is reduced by deactivating the clock signal on both the master and slave latches when there are no data transitions. The new circuit overcomes the clock duty-cycle constraints of previously proposed gated flip-flops. The power consumption of the presented circuit is significantly lower than that of a conventional flip-flop when the D input has a reduced switching activity     

TTL主从JK触发器在CP脉冲升降沿的工作特性研究

TTL主从JK触发器在时钟脉冲下降沿会出现输出状态异变，本文对这一问题进行了研究。