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本文提出了一种具有高k介质阶梯变宽度结构的新型的SOI LDMOS器件,该器件通过在漂移区内引入介质区域使得漂移区的宽度呈阶梯变化.借助三维器件仿真软件DAVINCI对其势场分布及耐压特性进行了深入分析.首先,阶梯变宽度结构能够在漂移区内引入新的电场峰值来优化势场分布,提高击穿电压.其次,采用高k材料作为侧壁介质区域可以进一步优化漂移区内势场分布,并提高漂移区浓度来降低导通电阻.结果表明,与常规结构相比,新器件的击穿电压可提高42%,导通电阻可降低37.5%,其FOM优值是常规器件的3.2倍. 相似文献
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围绕降低沟槽型SOI LDMOS功率器件的优值,提出了一种新型多栅沟槽 SOI LDMOS器件(MG-TMOS)。与常规沟槽型SOI LDMOS(C-TMOS)器件相比,新型MG-TMOS器件在不牺牲击穿电压的同时,降低了器件开关切换时充放电的栅漏电荷和器件的比导通电阻。这是因为:1) 新型MG-TMOS器件沟槽里的保护栅将器件的栅漏电容转换为器件的栅源电容和漏源电容,大幅度降低了器件的栅漏电荷;2) 保护栅偏置电压的存在使得器件导通时会在沟槽底部形成一层低阻积累层,从而降低器件的导通电阻。仿真结果表明:该新型沟槽型SOI LDMOS器件的优值从常规器件的503.4 mΩ·nC下降到406.6 mΩ·nC,实现了器件的快速关断。 相似文献
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近年来,随着汽车电子和电源驱动的发展,集成度较高的LDMOS作为热门功率器件受到了关注,如何提高其击穿电压与降低其比导通电阻成为提高器件性能的关键。基于SOI LDMOS技术,文章提出了在被4 μm的高K介质膜包围的SiO2沟槽中引入垂直场板的新型结构。与传统沟槽LDMOS相比,垂直场板和高K介质膜充分地将电势线引导至沟槽中,提高了击穿电压。此外垂直场板与高K介质和漂移区形成的MIS金属-绝缘层-半导体电容结构能增加漂移区表面的电荷量,降低比导通电阻。通过二维仿真软件,在7.5 μm深的沟槽中引入宽0.3 μm、深6.8 μm的垂直场板,实现了具有300 V的击穿电压和4.26 mΩ·cm2的比导通电阻,以及21.14 MW·cm-2的Baliga品质因数的LDMOS器件。 相似文献
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提出了一种新型D-RESURF埋栅SOI LDMOS (EGDR-SOI LDMOS)结构,其栅电极位于P-body区的下面,可以在扩展的埋栅电极处形成多数载流子的积累层;同时,采用Double- RESURF技术,在漂移区中引入两区的P降场层,有效降低了器件的比导通电阻,并提高了器件的击穿电压.采用二维数值仿真软件MEDICI,对器件的扩展栅电极、降场层进行了优化设计.结果表明,相对于普通SOI LDMOS,该结构的比导通电阻下降了78%,击穿电压上升了22%. 相似文献
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为了降低绝缘体上硅(SOI)功率器件的比导通电阻,同时提高击穿电压,利用场板(FP)技术,提出了一种具有L型栅极场板的双槽双栅SOI器件新结构.在双槽结构的基础上,在氧化槽中形成第二栅极,并延伸形成L型栅极场板.漂移区引入的氧化槽折叠了漂移区长度,提高了击穿电压;对称的双栅结构形成双导电沟道,加宽了电流纵向传输面积,使比导通电阻显著降低;L型场板对漂移区电场进行重塑,使漂移区浓度大幅度增加,比导通电阻进一步降低.仿真结果表明:在保证最高优值条件下,相比传统SOI结构,器件尺寸相同时,新结构的击穿电压提高了123%,比导通电阻降低了32%;击穿电压相同时,新结构的比导通电阻降低了87.5%;相比双槽SOI结构,器件尺寸相同时,新结构不仅保持了双槽结构的高压特性,而且比导通电阻降低了46%. 相似文献
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为了不增加器件成本,方便和低压器件集成到一起时实现自主隔离,因而迫切需要解决既能兼容普通半导体材料工艺又能达到相应技术性能要求的器件设计。为此设计了一种采用NWELL而非N-外延层作为nLDMOS的漂移区,在漏源极两端都加上了场极板的nLDMOS结构。而漂移区的结构及场极板设计是控制源漏击穿电压的关键。我们利用半导体工艺模拟软件Athena和Atlas着重对NWELL漂移区的长度、注入剂量、结深与器件的耐压关系以及场极板的长度与器件的耐压关系进行了模拟仿真。最后利用迭代法对这些参数进行了优化,得到了700V nLDMOS击穿电压的次优解。通过在CMOS工艺线上流片验证,得出此器件的耐压能达700V,与模拟仿真一致。 相似文献
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提出与CMOS工艺兼容的薄型双漂移区(TD)高压器件新结构.通过表面注入掺杂浓度较高的N-薄层,形成不同电阻率的双漂移区结构,改变漂移区电流线分布,降低导通电阻;沟道区下方采用P离子注入埋层来减小沟道区等位线曲率,在表面引入新的电场峰,改善横向表面电场分布,提高器件击穿电压.结果表明:TD LDMOS较常规结构击穿电压提高16%,导通电阻下降31%. 相似文献
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An improved high voltage LDMOSFET with multiple-resistivity drift region is proposed. Using the 2-D process simulator TSUPREM4 and device simulator MEDICI, we design a conventional LDMOSFET optimized for breakdown voltage. Then multiple-resistivity drift region is incorporated, with optimized thickness and doping concentration to reduce specific on-resistance while the breakdown voltage is not degraded. To further improve the device performance, we apply a field plate above the drift region to attract more electrons. Carrier concentration in the channel is increased, so drain current level is improved. The simulation result shows that the optimized complex structure, containing both multiple-resistivity drift region and a field plate, exhibits a 34.2% reduction in specific on-resistance with a mere 2.5% degradation of breakdown voltage compared to the standard LDMOSFET. 相似文献
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变漂移区厚度SOI横向高压器件的优化设计 总被引:1,自引:1,他引:0
提出了一种耐压技术——横向变厚度VLT技术,以及基于此技术的一种高压器件结构——变厚度漂移区SOI横向高压器件,借助二维器件仿真器MEDICI,深入研究了该结构的耐压机理。结果表明,变厚度漂移区结构不但可以使横向击穿电压提高20%,纵向击穿电压提高10%,而且可以使漂移区掺杂浓度提高150%~200%,从而降低漂移区电阻,使器件优值提高40%以上。进一步研究表明,对于所研究的结构,采用一阶或二阶阶梯作为线性漂移区的近似,可以降低制造成本,并且不会导致器件性能的下降。 相似文献
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Sang-Koo Chung Seung-Youp Han Jin-Cheol Shin Yearn-Ik Choi Sang-Bae Kim 《Electron Device Letters, IEEE》1996,17(1):22-24
An analytical model for calculating the minimum drift region length of SOI RESURF diodes is presented with an expression for the maximum breakdown voltage of the device. The minimum drift region length is determined from the condition that the maximum breakdown voltage due to the one-dimensional field along the vertical path equals that of the lateral electric field along the surface. Analytical results agree well with the simulations using PISCES II, and qualitatively with the experimental results 相似文献
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A new high-voltage LDMOS with folded drift region(FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance. 相似文献
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《Microelectronics Journal》2015,46(5):404-409
In this paper, a power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) on InGaAs is proposed to achieve substantial improvement in breakdown voltage, on-resistance and Baliga׳s figure-of-merit with reduced cell pitch. The proposed LDMOSFET contains two vertical gates which are placed in two separate trenches built in the drift region. The source and drain contacts are taken from the top. The modified device has a planer structure implemented on InGaAs which is suitable for medium voltage power integrated circuits. The performance of proposed device is evaluated using two-dimensional numerical simulations and results are compared with that of the conventional LDMOSFET. The proposed structure considerably reduces the electric field inside the drift region due to reduced-surface field (RESURF) effect even at increased doping concentration leading to improved design trade-off. The proposed device provides 144% higher breakdown voltage, 25% lower specific on-resistance, 8 times improvement in figure-of-merit, and 25% reduction in cell pitch as compared to the conventional device. 相似文献