基于量子细胞自动机的全加器实现

基于量子细胞自动机的双稳态特性和数字电路,设计了异或门和加法器,采用半经典仿真方法对其进行了仿真,并与Tougaw等人设计的异或门和全加器进行了比较,结果显示在能实现同样的异或和加法功能的情况下,电路结构较为简单且使用的QCA数目大大减少,在规模上只有Tougaw设计的电路的一半左右,这对于减小以后设计的更复杂电路的规模有较大的借鉴意义。     

基于扩展多染色体笛卡尔遗传规划的数字电路进化设计

针对多输出电路进化设计中出现的进化复杂度高及可能丢失潜在解的问题,提出了一种基于扩展多染色体笛卡尔遗传规划的数字电路进化设计方法。该方法采用基于输出分解的多染色体并行进化形式,并引入一种类似交叉功能的染色体操作方法,结合适应度评价扩展给出了与多染色体方法对应的（1＋A）扩展多染色体进化策略实现进化过程。较传统方法具有更少的计算工作量,且有效性受进化复杂度的影响较小,改善了进化设计方法的扩展性能。     

基于FPGA的数字电子钟设计

采用FPGA进行的数字电路设计具有更大的灵活性和通用性,已成为目前数字电路设计的主流方法之一.本文给出一种基于FPGA的数字钟设计方案.该方案采用VHDL设计底层模块,采用电路原理图设计顶层系统.整个系统在QuartusⅡ开发平台上完成设计、编译和仿真,并在FPGA硬件实验箱上进行测试.测试结果表明该设计方案切实可行.     

共振隧穿电路中翻转-传输代数系统的建立

在传统数字电路天关一信号理论的基础上.提出了一个全新的基于共振隧穿RT(Resonant Tunneling)电路的翻转-传输理论,建立了适用于共振隧穿电路的翻转-传输代数系统,确定了两种联结运算,并用共振隧穿器件实现了该两种联结运算的基本电路结构.为设计共振隧穿电路特别是基本逻辑电路提供了一个全新的理论基础和系统的设计方法.     

超高频RFID标签的数字电路设计

在研究读写器和射频标签通信过程的基础上,结合EPC C1G2协议以及ISO/IEC18000-6协议,采用VHDL语言设计出一种应用于超高频段的射频标签数字电路.对电路的系统结构和模块具体实现方法进行了描述.基于0.18 μm CMOS工艺标准单元库,采用EDA工具对电路进行了前端综合和后端物理实现.给出的仿真结果表明该电路符合协议要求,综合后的电路规模约为11000门,功耗约为35 μW.该电路可应用于超高频段的各种RFID标签的数字部分.     

基于CPLD的脉冲计数器设计

介绍了用CPLD HDL的EDA技术作为开发手段,实现对16通道脉冲信号计数的脉冲计数器的设计。该方法具有设计周期短,内部电路模块可移植的特点,解决了以往数字电路小规模多器件组合的设计瓶颈,经实际电路测试,该系统性能可靠。     

电磁场、电磁理论、电磁环境

0609094进化硬件在数字电路设计中的应用研究〔刊,中〕/李志立//航空计算技术.—2005,35(4).—1-3(L)进化硬件在航空航天电子系统中有巨大的应用价值和潜力。目前,电路进化设计是进化硬件研究的主要方向之一。本文介绍了进化硬件的原理,并针对平台中算法的早熟和收敛速度慢的缺点,改进了原有算法。同时,指出不同类型数字电路在进化中的区别,并以典型电路为例分别进行进化,对结果进行了比较分析,验证了所用算法进化不同类型电路的有效性。参40609095环境电磁场长时间数列分析=Analysis of long ti me se-ries of environmental electromagne…     

数字电路故障定位技术研究

针对当前常用电路故障定位技术的局限性,提出了一种基于电路功能的数字电路故障定位方法。通过适当的电路建模和测试程序集设计,逐步缩小故障电路范围,并最终实现故障准确定位。该建模方法具有建模简便、通用性强、易于计算机实现、具备自学习功能等优点,经实际工程验证是一种有效的数字电路故障定位方法。     

改进遗传算法在数字电路中的应用

为减少传统进化方法在数字电路设计出现的扩展性差和早熟收敛等问题,采用一种接近FPGA结构的遗传规划拓扑为模型,详细介绍了编码方案,通过真值比对和资源优化两方面对电路进行评价,结合最优保留策略和锦标赛法对遗传算法中选择算子进行改进。实验表明该方法有效保证种群多样性以及收敛性,对整合成复杂电路进行二次进化有一定意义。     

基于典型结构的电路自适应进化设计新方法

简述电路进化设计的基本原理和发展现状。针对制约进化设计速度和规模的主要因素，提出并讨论一种基于典型电路结构、PSPICE仿真和遗传参数自适应的改进方法。有源滤波器等的进化实验结果表明，该方法支持对元件参数和电路结构的同时进化，并可显著加快进化速度。     

The new possibilities of telephone switching

Switching system architectures have evolved to be responsive to the needs of the user. Their design has been constrained by the existing environment which treats terminals, transmission channels, and switching entities as separate "black boxes." Telephone switching circuits have used relatively expensive discrete components, and hence, system designers used common control techniques to minimize the system cost. This was done by providing the circuits in common whenever this was possible. Such common circuits were associated with a switched path for the period of time for which the functions of the circuit were required. This was followed by "one at a time" operation and by the use of stored program controls. The advent of low-cost electronic circuit components has resulted in the application of digital techniques to switching systems. For the first time, the combination of switching and transmission is possible. This is the near-term objective. The long-term objective, made possible by forecasts of low-cost memory and electronic gate circuits, is the combination of switching, transmission, and the terminals. This will result in much more complex terminals.     

Picosecond optical sampling of GaAs integrated circuits

Direct electrooptic sampling is a noncontact optical-probing technique for measuring with picosecond time resolution the voltage waveforms at internal nodes within GaAs integrated circuits. The factors contributing to system bandwidth, sensitivity, spatial resolution, and circuit perturbation are discussed, as are the circuit requirements for realistic testing of analog and digital devices. Measurements of high-speed GaAs integrated circuits are presented, including time-domain waveform and timing measurements of digital and analog circuits and frequency-domain transfer function measurements of microwave circuits and transmission structures     

CMOS图像传感器中数字噪声抑制技术研究

设计了一种可以降低CMOS图像传感器(CIS)中数字噪声对模拟信号影响的时序.在时序控制电路中加入了门控时钟,使数字电路各模块可分时工作,在模拟电路采样阶段保持静止以抑制噪声.理论分析和测试结果表明,采样阶段噪声减小70%,其他时间噪声减小20%.     

Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation

One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.     

Greedy hardware optimization for linear digital circuits usingnumber splitting and refactorization

A greedy optimization technique for minimizing the area of linear digital systems using a combination of common subexpression elimination and modification of multiplier coefficients is proposed. Since the amount of logic required by a coefficient multiplier is dependent on the value of the coefficient, the given system is transformed, using splitting of coefficients, in such a way that the overall circuit requires a smaller area. The approach explores a much larger design space as compared to previously known techniques. The approach is the first to optimize numerically intensive digital circuits by additive decomposition of multiplier coefficients. The new synthesis scheme generates functionally equivalent but structurally different circuits with a 15 to 40% reduction in area over conventional methods, for practical circuits with DSP applications     

一种基于数字灰度的微显OLEDos的片上电路设计

介绍了高分辨率硅基微显OLED的特性和时间子场的数字灰度技术,基于单晶硅CMOS成熟技术,给出了一种片上电路设计方案,方案采用2管的数字像素电路,集成了行扫描电路及列数据驱动电路,经模拟仿真满足设计要求。     

基于FPGA的“数字电路”教学改革探索

传统“数字电路”课程以讲授中小规模电路为主,与产业和技术应用趋势严重脱节。本文以FPGA设计技术和硬件描述语言为基础,按照数字电路到复杂数字系统的顺序,从易到难地重新设计了教学内容,重点培养学生利用FPGA设计数字电路和数字系统的能力。在理论教学改革的同时,配套的实验课程也采用FPGA平台开展教学。课堂实践证明,改革后的新课程“数字电路与FPGA设计”能够满足应用型本科院校的人才培养需要。     

一种基于数字灰度的微显OLEDos的片上电路设计

介绍了高分辨率硅基微显OLED的特性和时间子场的数字灰度技术,基于单晶硅CMOS成熟技术,给出了一种片上电路设计方案,方案采用2管的数字像素电路,集成了行扫描电路及列数据驱动电路,经模拟仿真满足设计要求.     

具有OLED显示的智能化条纹相机(英文)

为了使条纹相机在一些特殊情况下能够使用良好,设计了一种基于PC-104、单片机8051和有机电致发光显示的智能化紫外皮秒条纹相机。相机的控制系统由数字化多扫速扫描电路、工作状态设置电路、像增强器选通电路和可程控化的高压供电系统构成。嵌入式PC-104通过控制I/O、A/D和D/A等接口来实现这些电路。该相机在自动调整参数、远程控制和系统自检方面都优于传统的相机。实验结果表明:控制系统稳定,时间分辨率优于100 ps,扫描非线性低于5%。     

The re-emission spectrum of digital hardware subjected to EMI

The emission spectrum of digital hardware under the influence of external electromagnetic interference is shown to contain information about the interaction of the incident energy with the digital circuits in the system. The generation mechanism of the re-emission spectrum is reviewed, describing how nonlinear effects may be a precursor to the failure of the equipment under test. Measurements on a simple circuit are used to demonstrate how the characteristics of the re-emission spectrum may be correlated with changes to the digital waveform within the circuit. The technique is also applied to a piece of complex digital hardware where similar, though more subtle, effects can be measured. It is shown that the re-emission spectrum can be used to detect the interaction of the interference with the digital devices at a level well below that which is able to cause static failures in the circuits. The utility of the technique as a diagnostic tool for immunity testing of digital hardware, by identifying which subsystems are being affected by external interference, is also demonstrated.