AlN陶瓷微热板MEMS传感器阵列设计与工艺实现

针对陶瓷基微热板MEMS器件难以微加工,器件表面加热Pt膜使用普通正性光刻胶难以实现光刻剥离的工艺难点问题,提出了激光微加工和柔性机械剥离相结合的微加工方法。以AlN陶瓷为衬底基片,采用激光微加工技术实现热隔离刻蚀体加工,刻蚀梁宽可达0.2 mm。采用柔性机械剥离工艺制备方法解决普通正性光刻胶形成倒梯形凹槽Pt膜难实现图形化问题,可在复杂表面特性的陶瓷基衬底上实现Pt膜剥离线宽10μm。同时利用有限元法进行传感器阵列设计和热结构仿真,验证设计工艺的可行性。     

Fabrication of a Fabry–PÉrot Cavity in a Microfluidic Channel Using Thermocompressive Gold Bonding of Glass Substrates

This paper presents a simple, low-cost, and reliable process for the fabrication of a microfluidic Fabry–PÉrot cavity in a Pyrex glass substrate. The microfluidic channels were etched in HF solution on a glass substrate using a Cr/Au/photoresist etching mask resulting in a channel bottom roughness of 1.309 nm. An effective thermocompressive gold–gold bonding technique was used to bond the photolithographically etched glass substrates inside a 350$^circ C $oven in a$ 10^ - 3~ torr $vacuum. Pressure was applied to the glass pieces by using two aluminum blocks with intermediate copper sheets. This method takes advantage of using Cr/Au layers both as a wet etching mask and as intermediate bonding layers, requiring only one lithography step for the entire process. The fabrication method is also compatible with the incorporation of dielectric mirror coatings in the channels to form a high-finesse Fabry–PÉrot cavity. A parallelism of 0.095 degrees was measured, and a finesse as high as 30 was obtained using an LED. The microfluidic cavity developed here can be used in electrophoresis and intracavity spectroscopy experiments.hfillhbox[1375]     

ICP深硅刻蚀工艺掩模的研究

通过使用深硅等离子刻蚀机,以C4 F8和SF6为刻蚀气体,对以光刻胶与金属铝两种材料作为掩模的深硅刻蚀结果进行对比,研究了深硅刻蚀过程中掩模材料对刻蚀结果的影响。实验结果表明：以光刻胶做掩模,深硅刻蚀后硅侧壁和硅底部表面形貌平整,垂直度较之铝掩模相当;以金属铝做掩模,深硅刻蚀后深槽底部表面不平整,出现长草现象,但是刻蚀选择比大于光刻胶,两种掩模的硅刻蚀速率相当。     

Lithography with high depth of focus by an ion projection system

Ion projection lithography is developed to generate structures with minimum feature sizes in the 100-nm range with a high pixel transfer rate. The high depth of focus (DOF) resulting from the telecentric beam path concept is also noteworthy. A silicon wafer exhibiting 200-μm-deep cavities, which are fabricated by anisotropic etching, is patterned with a grating of 0.6 μm periodicity running with identical spacings from the bottom to the top. SiO₂ serves as an inorganic ion sensitive resist. Exposed to 73 keV helium ions, SiO₂ shows an enhanced etching rate in hydrofluoric acid, the structure developing agent. The patterning techniques considered are promising for the fabrication of two-dimensional reflecting mirrors or sensoric elements distributed on spherical surfaces     

Simulation of deep UV lithography with SU-8 resist by using 365 nm light source

The deep lithography of thick resist layer is the primary step of LIGA technology. UV Proximity lithography, which is used to fabricate high aspect ratio MEMS normally, is investigated in this paper. The light intensity distribution in the thick photoresist layer mainly depends on the diffraction produced by the gap between mask and wafer in proximity lithography. Fresnel diffraction model is used to simulate lithography process normally, which the thin photoresist layer is used in the lithography process. But it is not accurate in deep lithography process. A correction to the Fresnel diffraction theory is used to simulate the lithography process depending on the scalar diffraction theory of light propagation in this paper. The difference of this two models is given in this paper. The simulation results show that the corrected model can obtain more accurate simulation results than the Fresnel diffraction model. The experiment results and the theory analysis both indicate that: the structure contrast decreases with the increase of the film thickness. The smaller the structure linewidth is, the faster the structure contrast decreases. The linewidth of microstructure is not equivalent from the top to the bottom, broaden in the middle part normally. The theory simulation gives the quantitative analysis.This work was supported by of China 973 Program (No. 1999033109).     

Patterning of burnishing head for hard disk platters by synchrotron radiation lithography

This paper discusses the patterning of the burnishing head for hard disk platters on the AlTiC substrate, performed by X-ray exposure through X-ray mask to identify areas still left on the substrate after the photoresist development. The high energy and the low divergence of the synchrotron light provided the high-aspect-ratio microstructures with high accuracy patterns of burnishing head specifications. After the X-ray lithography was processed, the AlTiC substrate coated with the SU-8 hard mask was dry-etched with CF₄ of the RIE machine and run under the various conditions of the industrial process. An appropriate condition based on a total of 10 experimental conditions, which were based on the CCD technique, was investigated at Minitab using the data collected for analysis and compared with the standard specification. Based on the standard specification of the critical dimension of 8.02 µm and the etched depth of 30.0 µm, the best condition for the experiment, calculated by the desirability approach, was the 250 µm-thick SU-8 photoresist with an exposure dose of 23,010 mJ/cm³ and an RIE etching time of about 20 h. Mathematically, this condition offers a critical dimension and an etched depth of 7.02 and 30.11 µm, respectively. When the actual experiment was conducted to confirm the results, and we found that the critical dimension and the etched depth showed values of 7.03 and 30.02 µm, respectively.     

Etching processes for High Aspect Ratio Micro Systems Technology (HARMST)

 This paper reports on the development of a dry etching based HARMS-Technology which will offer the potential to manufacture micro-engines, micro-turbines, micro-sensors, micro-actuators, and electronic circuits onto a single silicon IC chip. This technology is based on the highly anisotropic and selective dry etching of Si-monocrystals. The suitability of reactive ion etching for the fabrication of micro electro mechanical systems (MEMS) has been evaluated by characterising the change of lateral dimensions vs. depth in etching deep structures in silicon. Fluorine, chlorine and bromine containing gases have provided the basis for this investigation. A conventional planar RIE (Reactive Ion Etching) reactor has been used, in some cases with magnetic field enhancement or ICP (Inductive Coupled Plasma) Source and low substrate temperature. For reactive ion etching based on Cl₂ or Cl₂/HBr plasma a slightly “positive” (top wider than bottom) slope is achieved when etching structures with a depth of several 10 μm, whereas a “negative” slope is obtained when etching with an SF₆/CCl₂F₂ based plasma. Pattern transfer with vertical walls is obtained for reactive ion etching based on SF₆ (with O₂ added) when maintaining the substrate at low temperature (in range ≈−100 °C). Further optimisation of plasma chemistries and reactive ion etching procedures should result in runouts in the order or 0.1 μm/100 μm depth in Si as well as in organic materials. Etching processes for HARMST is demonstrated in the realisation in Si microturbine. Axes or stators (nonmoving parts) are etched into the initial Si-wafer. The movable parts (rotors, beams, etc.) are prepared from electro-chemically etched Si-membranes with defined thicknesses that, all movable parts are created lithographically on the SiN_xO_y surface. This is followed by dry etching the mono-crystalline Si-membrane down to the SiN_xO_y sacrificial layer on the back side of the membrane by an RIE-process. The wafer with the movable parts is flipped onto the wafer with the already etched axis and then positioned and centred. The SiN_xO_y-sacrificial layer is then dissolved by a chemical wet or vapour etch process. Subsequent bonding with a Pyrex glass wafer seals the parts. Received: 30 October 1995/Accepted: 20 May 1996     

Shallow and deep dry etching of silicon using ICP cryogenic reactive ion etching process

We achieved to etch nanostructures as well as structures with high aspect ratios in silicon using an inductively coupled plasma cryogenic deep reactive ion etching process. We etched cantilevers, submicron diameter pillars, membranes and deep structures in silicon with etch rates between 13 nm/min and 4 μm/min. These structures find applications as templates for metal organic vapour phase epitaxial growth of GaN-based nanostructures for optoelectronic devices or they are the basic constituents of a nanoparticle balance in the subnanogram range and of a thermoelectric generator.     

TMAH溶液中的(110)硅各向异性湿法腐蚀及其在不同添加剂下的腐蚀特性研究

研究了TMAH溶液中(110)硅片在不同几何形状掩膜窗口下的各向异性湿法腐蚀行为,探讨了(110)硅在TMAH与不同添加剂(过硫酸铵、异丙醇等)构成的腐蚀系统下的腐蚀特性.利用场发射扫描电子显微镜(SEM)观测(110)硅的腐蚀坑腔结构,利用扫描探针显微镜(SPM)测量(110)硅腐蚀的表面粗糙度.结果表明:(110)...     

Rapid soda-lime glass etching process for producing microfluidic channels with higher aspect ratio

This paper presents a simple method to produce microfluidic channels in soda-lime glasses with the aspect ratio >0.5 utilizing a modified wet etching protocol. A low-cost positive photoresist (PR) layer is used as the etching mask for the wet etching process. Prior to the PR and primer coating procedure, a UV activation process is adopted for enhancing the binding strength of the hexamethyldisilazane primer layer and the glass substrate, resulting in an better adhesion for the PR layer. A fast etching recipe is also developed by increasing the acidity and the temperature of the buffered oxide (BOE) etchant. Since the photoresist etching mask does not peel during the etching process shortly, the structure of the etching mask forms a barrier and results in a different diffusion rate for the etchant inside the etched trench structure. A slower etching rate for the glass is observed at the undercut region such that the proposed anisotropic etching pattern can be achieved. Results show that the etching rate of the modified glass etching process is as high as 7.7 μm/min which is much faster than that of pure BOE etchant (0.96 μm/min). Sealed microfluidic channel with the aspect ratio of around 0.62 is produced with the developed method. The method developed in the present study provides a rapid and efficient way to produce microfluidic channels with higher aspect ratio.     

Design and fabrication of an electrostatically suspended microgyroscope using UV-LIGA technology

A micromachined electrostatically suspended gyroscope, with a wheel-like rotor housed by top stator and bottom stator, using UV-LIGA microfabrication technology, was presented. The designed structure and basic operating principle of the gyroscope are described. The key steps in the fabrication process, such as wet etching of Pyrex glass pits for soldering, and integration of thick nickel structures by removal of SU-8 mold, were considered in detail and well solved. Cr/Pt/photoresist was used as etching mask and the etched pits, in depth of near 30 μm, with aspect ratio (depth to undercutting) of 0.75, were obtained. With metal foundations constructed for consolidation, successful integration of the nickel structures, in thickness of 200 μm, was achieved by successful removal of the SU-8 mold using oleum. After the two stators and the rotor were fabricated separately, they were assembled and soldering bonded to form axial and radial small gaps, hence, the initial prototype of the microgyroscope was realized. The key techniques described in this paper can be applied to fabrication of other micro devices. The metal foundation method, associated with removal of SU-8 mold by oleum, is expected to make SU-8 wider applications in making integrated microstructures with fabricated circuitry on the same chip.     

金属连线光刻技术

介绍了一种细线条金属连线光刻技术。在溅射铝后,生长一薄层氮化硅薄膜作为减反层,利用氮化硅薄膜的光刻条件,涂覆薄胶可以保证刻出细线条,腐蚀薄层氮化硅保证线宽,同时在腐蚀铝过程中用氮化硅作掩蔽解决了薄胶问题。并在亚微米的抗辐射加固电路中成功应用。     

Fabrication of Integrated Vertical Mirror Surfaces and Transparent Window for Packaging MEMS Devices

A scheme for creating metal-coated vertical mirrors in silicon, along with an integrated transparent package lid for assembling, packaging, and testing microelectromechanical systems (MEMS) devices is presented. Deep reaction ion etching (DRIE) method described here reduces the loading effect and maintains a uniform etch rate resulting in highly vertical structures. A novel self-masking lithography and liftoff process was developed to ensure that the vertical mirrors undergo uniform metallization while leaving a transparent window for optical probing. Front side of a Si wafer was shallow-etched using DRIE to define an eventual optical window. This surface was then anodically bonded to a Pyrex wafer. Backside Si was then patterned to define thin channels around the optical window. These channels were vertically etched using DRIE, after which the unattached portions of the window region were removed. Negative photoresist was spun on the remaining vertical structures and the stack was exposed from the Pyrex side using Si structures as a self-mask. Subsequent metal sputtering and liftoff results in the metallized top and mirror sidewalls while leaving a clear window. These integrated mirrors and lids are then bonded to the active MEMS mirrors. Various processes and results are illustrated with an example of packaged corner cube retroreflectors (CCRs)     

Hole-type two-dimensional photonic crystal fabricated in silicon on insulator wafers

We report the realization of two-dimensional (2D) photonic crystal (PhC) holes array using synthesized processing techniques of deep UV lithography, time-multiplexed reactive ion etching (TMRIE) and focus ion beam (FIB) etching. In this study, mixed density of holes and waveguide patterns of 2D PhC structures was first formed in silicon on insulator wafers through use of a scanner. Ultra wide grooves were then defined, aligned to the deep submicron size devices. Following deep etching of more than 50 μm by TMRIE, PhC structures were then revealed for device etching. Such design of fabrication process allows realization of disparate pattern dimensions and also etching depths. Through avoidance of etch lag effect, notching of devices at interface of device silicon and buried oxide layer was avoided. At the same time, through a singular FIB etch in the final step of the process following buried oxide release for PhC structures on critical dimension structures, severe loading effects of such structures were avoided to enable a wide process window of lithography and etch.     

Influence of residual layer on cross-sectional shape of thermal-reflowed photoresist structures

When photoresist structures are formed by employing various lithography technologies and followed by thermal reflow treatments, the mechanism that transforms the cross-section of a photoresist structure from a rectangular-shape into a circular-shape is seen as an integral constituent of the manufacturing method of microlens arrays. However, in the case, where a residual layer is absent, a photoresist film is completely exposed to the oncoming radiation down to the interface between the photoresist film and substrate. Even in the presence of a residual layer, it has been uncertain to the author if a photoresist structure with a circular cross-sectional shape could be obtained, and be made applicable for the fabrication of a microlens array. The author then executed a set of thermal reflow treatments under various conditions using a positive-tone photoresist AZP4903 known for its capability of forming relatively thick films. As a result, it became clear that the existence of a photoresist’s residual layer has large influence on the transformation of the cross-sectional shapes of photoresist structures. These observations can be attributed to whether the bottom surface of a photoresist structure is firmly fixed on a hard substrate, or if it happens to be in contact with a soft photoresist layer which can flow comparatively freely.     

Hydrogenation-Assisted Lateral Micromachining of (111) Silicon Wafers

Micromachining of (111) silicon wafers by means of a plasma hydrogenation and chemical etching sequence is achieved. Vertical etching is used to define the depth of the craters as well as the thickness of the final suspended silicon body. After protecting the 3-D structure by a thermally grown oxide, a hydrogenation step is used to remove the oxide layer from the bottom of the crater, allowing a lateral underetching. Final exposure of the processed silicon to a KOH solution, etches silicon in a lateral fashion and in the exposed places. A lateral aspect ratio of four to six has been achieved. The evolution of suspended structures on (111) wafers, suitable for sensor fabrication, is feasible without a need to a 3-D lithography. Using this technique suspended interdigital structures have been realized with a depth up to 70 $mu hbox{m}$. In addition, ultrathin fully suspended structures have been successfully fabricated. A preliminary capacitive accelerometer has been realized and tested on (111) substrate.$hfill$ [2008-0070]      

Asymmetric focusing microlens array fabricated using off-axis lithography

An asymmetric microlens with a given inclination angle was fabricated. Two circular pattern masks with different diameters were used to form a metal pattern and photoresist column on the substrate using the photolithography process. The metal pattern on the substrate was used to control the asymmetric microlens profile using thermal reflow. A lift-off process was applied to the first lithography to precisely define the metal pattern. A second lithography used deviation counterpoint exposure to pattern the photoresist column. The photoresist column was converted into a rubbery state when its temperature was increased to its glass transition temperature (Tg) during the thermal reflow. The asymmetric microlens structure was formed by shifting the arc vertex of the microlens toward one direction taking into account the fact that the copper coating surface has superior hydrophobicity to the silicon substrate surface. A 55° asymmetric microlens array was fabricated in this research by properly controlling the copper pattern size and the offset of two centers.     

Defect-free wet etching through pyrex glass using Cr/Au mask

This paper reports the highest etch depth of annealed Pyrex glass achieved by wet etching in highly concentrated HF solution, using a low stress chromium–gold with assistance of photoresist as masking layer. The strategies to achieve that are: increasing the etch rate of glass and simultaneously increasing the resistance of Cr/Au mask in the etchant. By annealing the Pyrex glass and using a highly concentrated HF acid, a high etch rate can be obtained. Furthermore, a method to achieve a good resistance of the Cr/Au masking layer in the etching solution is to control the residual stress and to increase the thickness of Au deposition up to 1 μm. In addition, the presence of a hard baked photoresist can improve the etching performance. As a result, a 500-μm thick Pyrex glass wafer was etched through.     

High-performance capacitive humidity sensor with novel electrode and polyimide layer based on MEMS technology

A high-performance capacitive humidity sensor based on a newly designed electrode and a polyimide (PI) layer is presented in this paper. The humidity sensor consists of a substrate with a cavity, a bottom electrode, a PI sensing layer, and a comb-shaped top electrode with branches. The cavity structure of the substrate was formed to protect the top electrode. In order to enhance the performance of the sensor, the coated PI layer was etched by using an O₂ plasma asher in accordance with the top electrode passivation. After the PI etching, the humidity sensor showed a high sensitivity of 506 fF/% RH and a fast response time of less than 6 s, which is attributed to the increased contact area between the PI layer and moisture, and shortened moisture absorption path into the PI layer. Further characterizations were carried out to measure the effect of temperature, hysteresis, and stability. The humidity sensor showed a hysteresis of 2.05% RH, little temperature dependence, and stable capacitance value with maximum 0.28% error rate for 24 h.