A low power CMOS compatible embedded EEPROM for passive RFID tag

A 512-bit low-voltage CMOS-compatible EEPROM is developed and embedded into a passive RFID tag chip using 0.18 μm CMOS technology. The write voltage is halved by adopting a planar EEPROM cell structure. The wide Vth distribution of as-received memory cells is mitigated by an initial erase and further reduced by an in-situ regulated erase operation using negative feedback. Although over-programmed charges leak from the floating gates over several days, the remaining charges are retained without further loss. The 512-bit planar EEPROM occupies 0.018 mm² and consumes 14.5 and 370 μW for read and write at 85 °C, respectively.     

应用于无源UHF RFID传感器接口的低功耗低压转换器设计

为了增加射频识别（RFID）传感器的识读范围,针对无源超高频（ultra high frequency,UHF）RFID标签的传感器接口,提出了一种新的低功耗低压时间数字转换器设计。该传感器接口采用基于游标原理的高效时数转换器,在保证分辨率和转换效率的同时,能够实现较低的功耗和较大的动态范围。采用TSMC 90nm标准CMOS技术设计并制造。测量结果显示相比其他类似结构,提出接口在输入时间范围28.18-42.94 时有效分辨率为10.48bits。采样率为20 KS/s时,转换器转化效率为0.396 pJ/bit,且功耗和电压供应分别仅为3.84 和0.6V,能够有效增强无源UHF RFID压力传感器标签的识读范围。     

CMOS power retriever for UHF RFID tags

A power retrieving circuit for a UHF RFID passive tag is proposed. The circuit is implemented with a 0.18 mum standard digital technology, and allows the empowering of the tag at more than 5 m from a 500 mW ERP interrogator.     

适用于EEPROM的低功耗高效率的高压产生电路

本文提出了一种应用于嵌入式EEPROM的低功耗和高效率的高电产生电路。低功耗的实现是基于电容分压电路和控制时钟的稳压电路技术;高效率是由于采用了零阈值Vth MOSFET和电荷传输开关技术的电荷泵。该高电压电路采用0.35 μm CMOS工艺流片。测试结果表明,高电产生电路的功耗约150.48 μW和电荷泵效率高达83.3％,因此高电产生电路也可广泛用于低功耗Flash中。     

Modeling and Design of CMOS UHF Voltage Multiplier for RFID in an EEPROM Compatible Process

Modeling and design of CMOS ultra-high-frequency (UHF) voltage multipliers are presented. These circuits recover power from incident radio frequency (RF) signal and supply battery less UHF RF identification (RFID) transponders. An analytical model of CMOS UHF voltage multipliers is developed. It permits to determine the main design parameters in order to improve multiplier performance. The design of this kind of circuits is then greatly simplified and simulation time is reduced. Thanks to this model, a voltage multiplier is designed and implemented in a low-cost electrically erasable programmable read-only memory compatible CMOS process without Schottky diodes layers. Measurements results show communication ranges up to 5 m in the U.S. standard.     

用于超高频标签芯片的低功耗高稳定时钟电路

提出一种适用于无源超高频射频识别(UHF RFID)标签芯片的时钟产生电路。电路使用N型金属-氧化物-半导体(NMOS)栅极电压取代了复杂的比较器电路作为比较电平,精简了电路结构,降低了电路功耗,减小了版图面积;使用二极管方式连接的NMOS管作温度及工艺补偿感应管,利用其栅压变化控制充放电电流,使其在不同工艺角下,当温度在较大范围内变化时,均能实现输出频率稳定。采用中芯国际0.18 μm工艺进行仿真验证,结果表明：当电源电压为1 V,基准电流为130 nA时,电路功耗仅为447 nW;在工艺角由ss变化到ff的过程中,输出频率偏差不超过2.43%,;温度在-40~90 ℃范围变化时,输出频率偏差小于0.99%,适合无源射频识别标签芯片使用。     

Design and analysis of a low power passive UHF RFID transponder IC

This paper presents a low power passive UHF RFID transponder IC, which is compatible with ISO/IEC 18000-6B Standard, operating at the 915 MHz ISM band with the total supply current consumption less than 10 μA. The fully integrated passive transponder, whose reading distance more than 3 m at 4 W (36 dBm) EIRP with an antenna gain less than 1.5 dBi, is powered by the received RF energy. There are no external components, except for the antenna. The transponder IC includes matching network, rectifier, regulator, power on reset circuit, local oscillator, bandgap reference, AM demodulator, backscatter, control logic and memory. The IC is fabricated using Chartered 0.35 μm two-poly four-metal CMOS process with Schottky diodes and EEPROM supported. The die size is 1.5 mm × 1.0 mm.     

应用于UHF RFID标签的低功耗真随机数发生器

设计了一种基于振荡采样法的真随机数发生器.针对UHF RFID标签芯片功耗低、面积小的特点,利用简单有效的电路结构增强发生器的随机性.采用频率受控的被采样数据振荡器与采样时钟异或后形成初步随机数,并增加异或链输出负反馈结构,有效提高了输出序列中"0""1"分布的均匀性,降低了序列的自相关性.标签采用SMIC 0.18μm RF CMOS工艺设计并流片,采样时钟为2MHz,总工作电流少于2μA.     

超高频RFID读写器部分电路设计

本文以设计一种超高频射频读写器为目的,设计和实现了基于射频芯片Intel R1000和微控制器AT91SAM9263的读写器系统,增加了外部PA设计,从而大大提高了读写器的读写距离。     

A low cost integrated transceiver for mobile UHF passive RFID reader applications

2.5 mm2 including pads.     

一款便携式移动应用的低成本超高频无源射频识别读写器收发机芯片设计

A low cost integrated transceiver for mobile UHF passive RFID reader applications is implemented in a 0.18μm CMOS process. The transceiver contains an OOK modulator and a power amplifier in the transmitter chain, an IQ direct-down converter, variable-gain amplifiers, channel-select filters and a 10-bit ADC in the receiver chain. The measured output PldB power of the transmitter is 17.6 dBm and the measured receiver sensitivity is -70 dBm. The on-chip integer N synthesizer achieves a frequency resolution of 200 kHz with a phase noise of -104 dBc/Hz at 100 kHz frequency offset and -120.83 dBc/Hz at 1 MHz frequency offset. The transmitter, the receiver and the frequency synthesizer consume 201.34, 25.3 and 54 mW, respectively. The chip has a die area of 4 × 2.5 mm^2 including pads.     

Low‐Power 512‐Bit EEPROM Designed for UHF RFID Tag Chip

In this paper, the design of a low‐power 512‐bit synchronous EEPROM for a passive UHF RFID tag chip is presented. We apply low‐power schemes, such as dual power supply voltage (VDD=1.5 V and VDDP=2.5 V), clocked inverter sensing, voltage‐up converter, I/O interface, and Dickson charge pump using Schottky diode. An EEPROM is fabricated with the 0.25 μm EEPROM process. Power dissipation is 32.78 μW in the read cycle and 78.05 μW in the write cycle. The layout size is 449.3 μm × 480.67 μm.     

一种应用于超高频RFID的自干扰抵消电路

提出了一种应用于超高频RFID的集成自干扰抵消电路,它主要由一个6位有源移相器、一个3位可控增益功率放大器和缓冲器组成。有源移相器采用可降位的编码方式,简化了数字逻辑。可控增益功率放大器通过采用电容补偿技术和偏置点的优化选取来提高线性度。该自干扰抵消电路在130 nm CMOS工艺下实现,采用1.5 V和3.3 V双电源供电。后仿真结果显示,针对8 dBm的自干扰信号,该电路在840~940 MHz带宽内的自干扰抑制比大于28 dB。     

Ultra-low power PSK backscatter modulator for UHF and microwave RFID transponders

An integrated circuit implementation of a PSK backscatter modulator for passive radio frequency identification (RFID) transponders is proposed. Such modulator offers a significant reduction of the power consumption with respect to other schemes already presented in the literature. Furthermore, the topology of the proposed modulator allows us to control its output resistance so that only a negligible fraction of the active power at the antenna goes to the modulator.     

A read disturbance free differential read SRAM cell for low power and reliable cache in embedded processor

Energy consumption and data stability are vital requirement of cache in embedded processor. SRAM is a natural choice for cache memory owing to their speed and energy efficiency. Noise insertion to the SRAM cell during read is a serious problem which reduces its stability. A read disturbance free differential SRAM cell consisting of seven transistors is proposed here which increases cell stability along with maintaining the most desirable differential read technique for faster read. The read SNM of the proposed cell is 154%, 31% and 58% large than that of the conventional 6T-SRAM cell and 2 other 7T-SRAM cells [5,6] compared here. Various factors such as short circuit current reduction, use of single write access transistor, partial bit line swing etc. reduces the overall energy consumption of the proposed cell by 41% compared to 6T-SRAM cell. The proposed cell is also compared with an eight transistor based read disturbance free SRAM cell. The cell delay of the proposed cell is around 55% lesser than that of the 8T-SRAM cell. Besides CMOS the performance achievement of the proposed 7T-SRAM cell is also validated at miniaturized dimension of 20 nm using FinFET based predictive technology model library.     

An EEPROM Programming Controller for Passive UHF RFID Transponders With Gated Clock Regulation Loop and Current Surge Control

This paper presents an EEPROM programming controller imbedded in a passive UHF RFID transponder. A 14 V programming voltage is generated and regulated for a 224-bit EEPROM memory array from a rectified voltage supply of 2–3 V. A gated clock regulation loop is proposed to keep the programming voltage constant over a wide range of received RF input power, in order to improve the write–erase endurance of the memory. A current surge control scheme is proposed to allow the EEPROM programming voltage ramping in steps, therefore, preventing the collapse of the rectified supply in the remotely powered transponder. Also presented is a nano-power switched bandgap reference to reduce die area through the reduction of M$Omega$ resistors needed for nano-power operation. Measurement results show that a 0.35 $mu{hbox {m}}$ CMOS transponder IC provides a stable EEPROM programming voltage which varies less than 8% over a large 30 dB input power range while consuming 7 $mu{hbox{W}}$. The EEPROM programming controller occupies 0.092 ${hbox {mm}}^{2}$ die area.      

一种超高频射频识别天线的设计

随着射频识别(Radio Frequency Identification,RFID)技术的快速发展,提出了一款应用于RFID读写器的微带圆极化天线,该设计通过采用矩形微带贴片切角和电容耦合馈电技术实现了圆极化、宽频带特性,通过理论分析、计算、软件仿真以及加工测量等手段进行实验验证,实验结果表明该天线达到了设计要求指标,可广泛应用于超宽带无线通信领域中。     

Modeling and analysis of power extraction circuits for passive UHF RFID applications

Modeling and analysis of far field power extraction circuits for passive UHF RF identification (RFID) applications are presented. A mathematical model is derived to predict the complex nonlinear performance of UHF voltage multiplier using Schottky diodes. To reduce the complexity of the proposed model, a simple linear ap-proximation for Schottky diode is introduced. Measurement results show considerable agreement with the values calculated by the proposed model. With the derived model, optimization on stage number for voltage multiplier to achieve maximum power conversion efficiency is discussed. Furthermore, according to the Bode-Fano criterion and the proposed model, a limitation on maximum power up range for passive UHF RFID power extraction circuits is also studied.