Critical conditions of saddle-node bifurcations in switching DC–DC converters

Although existence of multiple periodic orbits in some DC–DC converters have been known for decades, linking the multiple periodic orbits with the saddle-node bifurcation (SNB) is rarely reported. The SNB occurs in popular DC–DC converters, but it is generally reported as a strange instability. Recently, design-oriented instability critical conditions are of great interest. In this article, average, sampled-data and harmonic balance analyses are applied and they lead to equivalent results. Many new critical conditions are derived. They facilitate future research on the instability associated with multiple periodic orbits, sudden voltage jumps or disappearances of periodic orbits observed in DC–DC converters. The effects of various converter parameters on the instability can be readily seen from the derived critical conditions. New Nyquist-like plots are also proposed to predict or prevent the occurrence of the instability.     

Fast-transient techniques for high-frequency DC–DC converters

A 30 MHz voltage-mode controlled buck converter with fast transient responses is presented. An improved differential difference amplifier (DDA)-based Type-III compensator is proposed to reduce the settling times of the converter during load transients, and to achieve near-optimal transient responses with simple PWM control only. Moreover, a hybrid scheme using a digital linear regulator with automatic transient detection and seamless loop transition is proposed to further improve the transient responses. By monitoring the output voltage of the compensator instead of the output voltage of the converter, the proposed hybrid scheme can reduce undershoot and overshoot effectively with good noise immunity and without interrupting the PWM loop. The converter was fabricated in a 0.13 µm standard CMOS process using 3.3 V devices. With an input voltage of 3.3 V, the measured peak efficiencies at the output voltages of 2.4, 1.8, and 1.2 V are 90.7%, 88%, and 83.6%, respectively. With a load step of 1.25 A and rise and fall times of 2 ns, the measured 1% settling times were 220 and 230 ns, with undershoot and overshoot with PWM control of 72 and 76 mV, respectively. They were further reduced to 36 and 38 mV by using the proposed hybrid scheme, and 1% settling times were also reduced to 125 ns.     

Novel bidirectional DC–DC converters based on the three-state switching cell

It is well known that there is an increasing demand for bidirectional DC–DC converters for applications that range from renewable energy sources to electric vehicles. Within this context, this work proposes novel DC–DC converter topologies that use the three-state switching cell (3SSC), whose well-known advantages over conventional existing structures are ability to operate at high current levels, while current sharing is maintained by a high frequency transformer; reduction of cost and dimensions of magnetics; improved distribution of losses, with consequent increase of global efficiency and reduction of cost associated to the need of semiconductors with lower current ratings. Three distinct topologies can be derived from the 3SSC: one DC–DC converter with reversible current characteristic able to operate in the first and second quadrants; one DC–DC converter with reversible voltage characteristic able to operate in the first and third quadrants and one DC–DC converter with reversible current and voltage characteristics able to operate in four quadrants. Only the topology with bidirectional current characteristic is analysed in detail in terms of the operating stages in both nonoverlapping and overlapping modes, while the design procedure of the power stage elements is obtained. In order to validate the theoretical assumptions, an experimental prototype is also implemented, so that relevant issues can be properly discussed.     

Favorable basic cells for hybrid DC–DC converters

<正>With the surging demands for extremely high current at sub-1 V supply voltage level in high performance computing and autonomous driving, high density power delivery becomes one of the critical limiting factors for system integration. 48 V power bus system is emerging for these high current applications to reduce the IR losses on the power delivery networks. Thus,     

A design methodology for integrated inductor-based DC–DC converters

A design methodology for monolithic integration of inductor based DC–DC converters is proposed in this paper. A power loss model of the power stage, including the drive circuits, is defined in order to optimize efficiency. Based on this model and taking as reference a 0.35 μm CMOS process, a buck converter was designed and fabricated. For a given set of operating conditions the defined power loss model allows to optimize the design parameters for the power stage, including the gate-driver tapering factor and the width of the power MOSFETs. Experimental results obtained from a buck converter at 100 MHz switching frequency are presented to validate the proposed methodology.     

Design and implementation of adaptive slope compensation in current mode DC–DC onverter

To improve the compensation for the inherent instability in a current mode converter, the adaptive slope compensation, giving attention to the problems of the traditional compensation on compensation accuracy, loading capability and turning jitter, is presented. Based on the analysis of current loop, by detecting the input and output voltage, converting the adaptive slope compensation current, the compensation of the current loop is optimized successfully. It can not only improve the compensation accuracy but also eliminate the over compensation, the turning jitter and the poor loading capability in the reported slope compensation. A power supply chip with adaptive slope compensation has been fabricated in a 0.35 μm CMOS process. The measurement results show that the chip starts up and operates steadily with the constant current limit under conditions of 5 V input voltage, from 10% to 100% duty cycle.     

Digital modular control of high frequency DC–DC converters

This paper presents a solution for controlling integrated DC–DC converters with high switching frequency (>20 MHz). The increase of the switching frequency is a trend biased by output filter volume restrictions and integration demand. The control of DC–DC converters operating at high frequency presents an opportunity to speed up the converter response time but also a challenge specially for the control solution, quiescent current and to limit the sensitivity to process and operating conditions for the mixed signal circuits involved. The solution presented in this work relies on separating the duty-cycle into three parts: a load-free value that depends only on the input and output voltages, a transient fast correction contribution, and an accurate compensation for the IR drop that depends on the load current. The load-free portion of the duty-cycle has a compensation of PVT variations and the fast transient part of the duty-cycle uses a non-linear sliding mode control solution. All the analog blocks required for the implementation of the proposed solution are detailed.     

A brief review of models of DC–DC power electronic converters for analysis of their stability

A brief review of models of DC–DC power electronic converters (PECs) is presented in this paper. It contains the most popular, continuous-time and discrete-time models used for PEC simulation, design, stability analysis and other applications. Both large-signal and small-signal models are considered. Special attention is paid to models that are used in practice for the analysis of the global and local stability of PECs.     

Analysis of high voltage step-up nonisolated DC–DC boost converters

A high voltage step-up nonisolated DC–DC converter based on coupled inductors suitable to photovoltaic (PV) systems applications is proposed in this paper. Considering that numerous approaches exist to extend the voltage conversion ratio of DC–DC converters that do not use transformers, a detailed comparison is also presented among the proposed converter and other popular topologies such as the conventional boost converter and the quadratic boost converter. The qualitative analysis of the coupled-inductor-based topology is developed so that a design procedure can be obtained, from which an experimental prototype is implemented to validate the theoretical assumptions.     

Design and implementation of a switched capacitor-based embedded hybrid DC–DC converter

The binary coded form of minterms for both minterms and reduced minterms is used in a very simple method for searching for prime implicants of logic functions. It only requires XOR and comparison operations.     

Design of a low-power 8 × 8-bit parallel multiplier using MOS current mode logic circuit

This paper proposes an 8?×?8 bit parallel multiplier using MOS current mode logic (MCML) for low power consumption. The 8?×?8 bit multiplier is designed with the proposed MCML full adders and the conventional full adders. The proposed multiplier is achieved to reduce the power consumption by 9.4% and the power-delay-product by 11.7% compared with the conventional circuit. The validity and effectiveness are verified through HSPICE simulation. The proposed multiplier is designed with the Samsung 0.35?μm standard CMOS process.     

Adaptive duty ratio modulation technique in switching DC–DC converter operating in discontinuous conduction mode

Adaptive duty ratio (ADR) modulation technique in switching DC–DC converter operating in discontinuous conduction mode is proposed in this paper. The proposed ADR modulation technique can regulate the output voltage of the DC–DC converter by generating a series of duty ratios with very simple circuit architecture. The duty ratio is approximately proportional to the square root of the voltage difference between the regulated output voltage and the reference voltage at the beginning of the switching cycle at the light load. As a result, the proposed ADR modulation technique can achieve smaller ripple than the conventional pulse skip modulation over the whole load range. Moreover, the compromise between the light-load ripple and the output power range in the design stage in previous works is solved in the ADR modulation technique. Theoretical analysis, simulation and experimental results are presented to show the operation principle and the advantage of the proposed ADR modulation technique.     

A voltage mode buck DC–DC converter with automatic PWM/PSM mode switching by detecting the transient inductor current

This paper presents a voltage mode buck DC–DC converter that integrates pulse-width modulation (PWM) and pulse-skipping modulation (PSM) to achieve high efficiency under heavy and light load conditions, respectively. Automatic mode-switching is implemented simply by detecting the voltage drop of high-side power switch when it is on, which indicates the transient current flowing through the inductor. Unlike other methods based on average current sensing, the proposed auto-mode switching scheme is implemented based on voltage comparison and simple control logic circuit. In order to avoid unstable mode switching near the load condition boundary, the mode switching threshold voltage is set differently in PWM and PSM mode. Besides, a 16-cycle counter is also used to ensure correct detection of the change in the load condition and fast response of the converter. In addition, a dual-path error amplifier with clamp circuit is also adopted to realize loop compensation and ensure 100 % duty cycle operation. Fabricated in a 0.18-μm standard CMOS technology, the DC–DC converter is able to operate under supply voltage from 2.8 to 5.5 V with 3-MHz clock frequency. Measurement results show that the converter achieves a peak efficiency of 93 %, and an output voltage ripple of less than 40 mV, while the chip area is 1.02 mm².     

Cascade controller with sliding-mode-voltage and current-mode for monolithic high frequency DC–DC converters

Modern control theories such as fuzzy control, sliding-mode control, optimal control, neural network control have been widely used in discrete-switching DC–DC converters, While they are seldom used in monolithic integration. Under parameter variation, large supply and load disturbance, high slew-rate current transient, high nonlinearity in today and future power management integrated circuits, linear control theories used in traditional monolithic DC–DC converters cannot satisfy required performance, which make it stringent to use modern control theories in monolithic DC–DC converters. This paper proposes cascade controller which consists of PWM based sliding-mode-voltage control and current-mode control for high frequency DC–DC converters. As long as the dynamic responses of the inner current loop are much faster than the outer sliding-mode-voltage loop, inner and outer loops operate in cascade-mode functionally. This work leads to an easy-to-follow design procedure to design control coefficients. To illustrate the feasibility of the scheme, a monolithic 100 MHz boost DC–DC converter using cascade controller with sliding-mode-voltage and current-mode is designed in SMIC 0.18 μm CMOS process. Several simulations are performed to validate the functionalities of the controller.     

Trajectory prediction control for digital control DC–DC converters with fast transient response

A novel trajectory prediction control algorithm for digital control DC–DC converters has been presented in this paper. The proposed trajectory prediction control algorithm can provide an accurate prediction of the duty ratio of the next several switching cycles, so as to overcome the inherent time delay of the digital control loop, and to improve the transient response of digital control DC–DC converters, including load response, line response and reference tracking response. A digital control buck DC–DC converter was implemented to verify the effectiveness of the proposed prediction control algorithm. The recovery time is about 8 μs and 4 μs respectively, when the load current changes from a full load to a 17% load and the input voltage changing between 5 V to 6 V. The fastest reference tracking speed is about 26.7 μs/V.     

Finite-time control of DC–DC buck converters via integral terminal sliding modes

This article presents novel terminal sliding modes for finite-time output tracking control of DC–DC buck converters. Instead of using traditional singular terminal sliding mode, two integral terminal sliding modes are introduced for robust output voltage tracking of uncertain buck converters. Different from traditional sliding mode control (SMC), the proposed controller assures finite convergence time for the tracking error and integral tracking error. Furthermore, the singular problem in traditional terminal SMC is removed from this article. When considering worse modelling, adaptive integral terminal SMC is derived to guarantee finite-time convergence under more relaxed stability conditions. In addition, several experiments show better start-up performance and robustness.     

Analysis of stepwise charging limits and its implementation for efficiency improvement in switched capacitor DC–DC converters

In this work we analysed the stepwise charging technique to find the limits from which it is beneficial in terms of load capacitance and charge–discharge frequency. We included in the analysis practical limitations such as the consumption of auxiliary logic needed to implement the technique and the minimum size of auxiliary switches imposed by the technology. We proposed an ultra-low-power logic block to push these limits and to obtain benefits from this technique in small capacitances. Finally, we proposed to use a stepwise driver in the driving of the gate capacitance of power switches in switched-capacitor (SC) DC–DC converters. We designed and manufactured, in a 130 nm process, a SC DC–DC converter and measured a 29% energy reduction in the gate-drive losses of the converter. This accounts for an improvement of 4% (from 69 to 73%) in the overall converter efficiency.

     

A novel PWM control for a bi-directional full-bridge DC–DC converter with smooth conversion mode transitions

A novel CMOS integrated pulse-width modulation (PWM) control circuit allowing smooth transitions between conversion modes in full-bridge based bi-directional DC–DC converters operating at high switching frequencies is presented. The novel PWM control circuit is able to drive full-bridge based DC–DC converters performing step-down (i.e. buck) and step-up (i.e. boost) voltage conversion in both directions, thus allowing charging and discharging of the batteries in mobile systems. It provides smooth transitions between buck, buck-boost and boost modes. Additionally, the novel PWM control loop circuit uses a symmetrical triangular carrier, which overcomes the necessity of using an output phasing circuit previously required in PWM controllers based on sawtooth oscillators. The novel PWM control also enables to build bi-directional DC–DC converters operating at high switching frequencies (i.e. up to 10?MHz and above). Finally, the proposed PWM control circuit also allows the use of an average lossless inductor-current sensor for sensing the average load current even at very high switching frequencies. In this article, the proposed PWM control circuit is modelled and the integrated CMOS schematic is given. The corresponding theory is analysed and presented in detail. The circuit simulations realised in the Cadence Spectre software with a commercially available 0.18?µm mixed-signal CMOS technology from UMC are shown. The PWM control circuit was implemented in a monolithic integrated bi-directional CMOS DC–DC converter ASIC prototype. The fabricated prototype was tested experimentally and has shown performances in accordance with the theory.