在SOI基上设计实现D/A驱动的高压LDMOS开关电路

设计实现SOI基上带有D/A驱动的高压LDMOS功率开关电路,利用D/A变换的灵活性,运用数字电路与高压模拟电路混合设计方法,实现数字控制的耐压为300V的LDMOS功率开关电路．该功率集成电路芯片的实现,为SOI高压功率开关电路提供了一种更为方便快速的数字控制设计方法,同时也为功率系统集成电路提供了一种有效的实验验证,从而证实了功率系统集成的探索在理论上以及工程上具有一定的可行性．     

高压功率集成电路的混合模拟

提出了高压功率器件统一网络模型,并在SPICE3和PISCES2B的基础上,利用两级牛顿迭代法,开发了高压功率集成电路的电路——器件混合模拟软件.利用该软件对一个高压LDMOS开关电路进行了混合模拟.通过该种模式的模拟,能直接分析器件参数对电路性能的影响,为高压功率集成电路的设计提供了方便.     

铁氧体驱动与双路功率MOS单片集成电路研究

介绍了一种集成低压铁氧体驱动器和功率MOS管的单片集成电路。其内建驱动器工作电压9 V,功率MOS管极限电压大于80 V,工作电流3 A。该电路内含D/A转换器、双路比较器、触发器和组合逻辑电路,以及过频过压保护等功能,采用键合SOI深槽的CMOS/LDMOS工艺制作。     

基于自隔离技术的可集成SOI高压功率器件新结构

SOI功率器件的高耐压和高、低压间良好的隔离效果是SOI高压功率集成电路（SOI HVIC）的两项关键技术。本文提出在埋氧层（buried oxide layer,BOX）上表面处埋N岛 (buried n-islands,BNI) 的SOI LDMOS高压功率器件新结构,该结构采用自隔离技术使SOI HPIC中高压功率器件与低压控制电路单元之间达到理想的隔离效果。此外,N岛中的施主离子和位于耗尽N岛间的空穴使BOX层的电场强度从32V/μm增加到113V/μm,同时对漂移区表面电场分布进行调制,最终使器件击穿电压（BV）显著提高。实验测得一个BNI SOI LDMOS样品的耐压为673V,并在SOI HVPIC中表现出良好的隔离特性。     

新型功率器件SON-LDMOS的设计和研究

本文提出了一种新型的对称式SON LDMOS功率器件.在对器件击穿电压进行解析分析的基础上,利用Silvaco TCAD仿真软件Atals验证了漂移区设计对器件击穿电压的影响,证明了峰值击穿电压的存在.并且对比分析了SON　LD-MOS与SOI LDMOS击穿电压和寄生电容方面的优势,研究表明SON LDMOSD在击穿电压上比SOI LDMOS器件提高了近3倍,并且其寄生电容也较小,这为SON LDMOS在功率方面的应用提供了部分理论支持.     

漂移区为线性掺杂的高压薄膜SOI器件的研制

给出了漂移区为线性掺杂的高压薄膜SOI器件的设计原理和方法.在Si膜厚度为0.15μm、隐埋氧化层厚度为2μm的SOI硅片上进行了LDMOS晶体管的制作.首次对薄膜SOI功率器件的击穿电压与线性掺杂漂移区的杂质浓度梯度的关系进行了实验研究.通过对漂移区掺杂剂量的优化,所制成的漂移区长度为50μm的LDMOS晶体管呈现了高达612V的击穿电压.     

一种SOI CMOS/LDMOS单片智能功率集成电路

介绍了一种单片智能功率硅集成电路的设计和制造工艺，该电路包括工作于9V低压的常规CMOS管和两个最高耐压为80V、电流通过能力大于3A的LDMOS管。电路采用SOI介质隔离CMOS／LDMOS工艺，芯片面积约50mm^2。基于一种简单的二维模型，认为，在功率集成中，纵向导电的VDMOS管由于其导通电阻有一个自限制特点，因此并不特别适合智能功率集成。     

具有电阻场板的薄膜SOI-LDMOS的精确解析

介绍了一种对具有电阻场板的薄膜SOI LDMOS的精确解析设计方法.在对电场分析的基础上,提出了新的电离率模型,并求出了电离率积分的准确路径,进而得到击穿电压、漂移区掺杂、漂移区长度与SOI硅层厚度、埋氧层厚度的关系.模拟结果表明,解析与模拟结果具有很好的一致性,而且设计的器件具有击穿电压大、比导通电阻极小的优点.该解析理论为在薄膜SOI材料上制作性能优良的高压功率器件提供了一个很好的参考     

SOI LDMOS晶体管耐压结构的研究

SOI技术已经成功的应用到功率集成电路中,而击穿电压是功率器件一个重要的参数.本文对SOI LDMOS的击穿电压进行了分析,介绍了目前国内外几种典型的提高击穿电压的结构,较为详细的分析了RESURF原理的应用.     

高压功率集成电路的混合模拟

提出了高压功率器件统一网络模型 ,并在 SPICE3和 PISCES2 B的基础上 ,利用两级牛顿迭代法 ,开发了高压功率集成电路的电路——器件混合模拟软件 .利用该软件对一个高压 LD-MOS开关电路进行了混合模拟 .通过该种模式的模拟 ,能直接分析器件参数对电路性能的影响 ,为高压功率集成电路的设计提供了方便 .     

一款切合实际的30A能量计

本文介绍了一款集成了30A检测电阻器LTC2947.     

注钼纯铝的研究

利用从金属蒸汽真空弧离子源（简称ＭＢＶＶＡ源）引出的强束流钼离子对纯铝进行了不同束流密度的离子注入。加速电压为４８ｋＶ，剂量为３×１０￣（１７）ｃｍ￣（－２），束流密度为２５和４７μＡ·ｃｍ￣（－２），Ｘ衍射分析证明在注入层内可形成Ａｌ＿（１２）Ｍｏ晶体，背散射（ＲＢＳ）分析证明Ａｌ＿（１２）Ｍｏ的厚度可达６００至７００ｎｍ。     

A Nyquist-rate delta-sigma A/D converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time oversampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta-sigma modulators in parallel with no oversampling is similar to operating the same modulator with an oversampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require oversampling. Using this prototype, the design issues of the parallel delta-sigma A/D converter are explored and the theoretical performance with no oversampling and with low oversampling is verified. This architecture shows promise for obtaining high speed and resolution conversion since it retains much of the insensitivity to nonideal circuit behavior characteristic of the individual delta-sigma modulators     

A charge-domain D/A conversion system

In this article, a new multiplication type D/A conversion system using CCD is proposed and the result of simulations for evaluating its performance is reported. The system consists of a recursive charge divider which divides input charge-packet Qin sequentially into output charge-packets Qin · 2^-i and two charge-packet accumulators which accumulates output charge-packets from the recursive divider selectively according to digital input signal bits starting from MSB. The system converts input digital signal bit by bit, fully in charge-domain, thus the power consumption for this system is supposed to be very low. Also in this article, an effective method to achieve higher accuracy for splitting a charge-packet into two equal-sized packets using very simple hard-ware structure is proposed. As the result of simulations, we have found that the upper limit of accuracy for the conversion is determined by transfer efficiency of CCD, and within this range a trade-off relationship exists among conversion-accuracy, circuit-size and conversion-rate. This unique relationship enables to reduce the circuit size of D/A converter significantly maintaining the accuracy of conversion by slowing down the conversion-rate. This D/A converter is appropriate especially for the system integration because of its simple structure, tolerance to the fabrication error and low power consumption inherrent in the nature of CCD. By using of this system, it is expected to be possible to realize a focal plane image processor performing parallel analog operations such as DCT conversion with CCD imager incorporated on the same Si chip by the same MOS process technology.     

A monolithic video A/D converter

The design and measured performance of a fully parallel monolithic 8-bit A/D converter is reported. The required comparators and combining logic were designed and fabricated with a standard high-performance triple-diffused technology. A bipolar comparator circuit giving good performance with high input impedance is described. Circuit operation is reported at sample rates up to 30 megasamples per second (MS/s), with analog input signal power at frequencies up to 6 MHz. Full 8-bit linearity was achieved. An SNR of 42-44 dB was observed at input signal frequencies up to 5.3 MHz.     

高速高精度A/D转换器

本文介绍了用于观测太阳磁场的天文望远镜系统的高速高精度局部级联式多阈值A/D转换器。文章着重讨论了,为实现高速、高精度所采用的技术要点,并提出了研制高速高精度A/D转换器所必须考虑的有关问题。 我们所研制的A/D转换器,分辨率为1mV,相对误差0.025％,字长12位,前面接采样保持电路后,速度为10万次/秒。     

A charge-balancing monolithic A/D converter

The quest for a minimum-parts-count DPM led to the development of this monolithic, low power analog-to-digital converter. It incorporates the analog and digital functions historically implemented separately with specialized process technologies into a chip with full /spl plusmn/3 digit accuracy. The integration of resistors, compensation capacitors, and an oscillator reduces the external component complement to three capacitors and one adjustable reference. TTL compatible outputs include sign, overrange, and under range information in addition to the three digit strobes and the BCD data outputs. The logic operates between +5 V and ground, the linear section between +5 V and -5 V. The paper describes the conversion algorithm and its CMOS implementation, emphasizing the analog design of this innovative device.     

A Convenient Multivariate Gram-Charlier Type A Series

It is often necessary to approximate the probability density function of a random variable from given statistical moments. The Gram-Charlier Type A series is one well known method for such representations. In this note, the Gram-Charlier Type A series is generalized to the multidimensional case.     

一种识别说话者的新方法

在能够自动识别视频中的说话者的系统中,大部分采用的是声音和唇部运动相结合的方法。文中则采用了另一种方法有效地达到了目的,即通过检测人体头部和手部的运动来鉴别说话者。基于演讲者在说话时通常会伴有头部运动或是手部运动,该方法既能实现说话者的检测,又能避免由于观测点过远而导致无法判断人唇部运动的局限性。在系统的实施过程中,运用了多种图像处理方法,并且对三帧差运动法做出了改善,使其能更高效、更准确地检测到头部和手部的运动。经过多个不同的视频测试后,本系统的F1 score高达91．91％,从而验证了该系统的可行性。     

没有管理者的密钥共享方案

一般的密钥共享方案中都假设有一个管理者,管理者的作用是分发密钥,因此对管理者的可信要求很高,而现实生活中很难找到符合要求的管理者.文中利用单调存取结构上的张成方案构造了一个没有管理者的密钥共享方案,并证明其是一个可行的实用的密钥共享方案.基于这个的方案,构造了一个分布式密钥生成器.