利用改进的电荷泵法研究SONOS存储器陷阱电荷的分布特性

在silicon-oxide-nitride-oxide-silicon(SONOS)等电荷俘获型不挥发存储器中,编程操作后注入电荷的分布会对器件的读取、擦写以及可靠性带来影响.利用电荷泵方法可以有效而准确地测量出注入电荷沿沟道方向的分布.为了提高测试精度,在进行电荷泵测试时,采用固定低电平与固定高电平相结合的方法,分别对SONOS器件源端和漏端进行注入电荷分布的测试.通过测试,最终获得SONOS存储器在沟道热电子注入编程后的电子分布.电子分布的峰值区域在漏端附近,分布宽度在50nm左右.     

一种应用于纳米尺度器件陷阱电荷表征的新型改进电荷泵方法

随着器件特征尺寸的缩小,热载流子带来的器件蜕化效应越来越严重。电荷泵方法可用于表征陷阱电荷的分布。但由于局部阈值电压窄峰的影响,传统电荷泵法在测试陷阱电荷分布时存在误差。本文提出了一种改进型电荷泵测试方法,可用于精确提取纳米尺度器件中陷阱电荷的横向分布。 本文采用0.12微米的SONOS器件来验证这一方法的有效性。通过编程控制,使SONOS器件形成大约50纳米的阈值电压窄峰。采用新方法测试得到的陷阱电荷分布与测试得到的阈值电压有较好的一致性。     

N2O气氛退火对SONOS非易失性存储器性能的优化研究

SONOS(Silicon-Oxide-Nitride-Oxide-Silicon)型非易失性存储器件的电荷保持能力与Si-SiO2界面态的质量密切相关.通过在SONOS的隧穿氧化层工艺流程中增加适当的N2O退火工艺,改善了器件的擦除深度和编程速度,从而使得SONOS器件的存储器性能得到优化.通过进一步电荷泵测试表明,...     

一种基于电荷泵技术的界面态横向分布测量方法

本文以电荷泵技术为测量手段，结合数值计算，提出了一种新的测量界面态横向分布的方法．与传统方法相比具有理论模型较完善、测量中不引入新的蜕变、易于实现的特点，适用于研究短沟道器件的热载流子蜕变效应．用该方法对１．２μｍＬＤＤ结构ｎ－ＭＯＳＦＥＴ进行了研究，得到了应力后漏端附近产生的界面态的横向分布以及应力后阈值电压、平带电压的变化，并能确定由于热电子注入产生的氧化层陷阱电荷的数量和位置     

钝化层退火工艺引入的氢对P-Flash存储器耐久性的影响

研究了钝化层退火工艺引入的氢对P-Flash存储器耐久性的影响,建立了这一影响的物理模型,阐明了耐久性退化的机理。在四种不同测试条件下,对P-Flash存储器进行了编程/擦除的耐久性测试。测试结果表明,在高温且延时的条件下,器件的耐久性最差。耐久性与编程/擦除之间的延时相关,延时越长,耐久性衰减越严重。在器件编程后的延时过程中,SiO₂/Si界面处被氢原子钝化的硅悬挂键发生断裂。氢原子的不稳定性导致更多的界面陷阱电荷和氧化层电荷的产生,使得阈值电压负向偏移,造成负偏压温度的不稳定。通过优化BEOL工艺,可有效改善P-Flash存储器的耐久性。     

复合栅控二极管新技术提取热载流子诱生的NMOS/SOI器件界面陷阱的横向分布

提出了用复合栅控二极管新技术提取MOS/SOI器件界面陷阱沿沟道横向分布的原理,给出了具体的测试步骤和方法.在此基础上,对具有体接触的NMOS/SOI器件进行了具体的测试和分析,给出了不同的累积应力时间下的界面陷阱沿沟道方向的横向分布.结果表明:随累积应力时间的增加,不仅漏端边界的界面陷阱峰值上升,而且沿沟道方向,界面陷阱从漏端不断向源端增生.     

复合栅控二极管新技术提取热载流子诱生的NMOS/SOI器件界面陷阱的横向分布

提出了用复合栅控二极管新技术提取MOS/SOI器件界面陷阱沿沟道横向分布的原理,给出了具体的测试步骤和方法.在此基础上,对具有体接触的NMOS/SOI器件进行了具体的测试和分析,给出了不同的累积应力时间下的界面陷阱沿沟道方向的横向分布.结果表明:随累积应力时间的增加,不仅漏端边界的界面陷阱峰值上升,而且沿沟道方向,界面陷阱从漏端不断向源端增生.     

硅纳米晶粒基MOSFET存储器的荷电特征研究

本文研究了硅纳米晶粒MOSFET存储器的荷电特征.器件阈值电压偏移达1.8V以上,并随着沟道宽度的变窄而增加,而与沟道长度基本无关.同时,阈值涨落也随宽度的变窄而增大.在20~300K测量温度范围内,器件阈值偏移和电荷的存储特性几乎不随温度变化,说明荷电过程主要由直接隧穿决定.进一步,在最窄沟道器件中观察到单电荷的荷电过程.     

SCDI结构快闪存储器件Ⅰ:模拟与分析

研制成一种台阶沟道直接注入(SCDI)器件,通过在沟道的中间制作一个浅的台阶来改变热载流子的注入方式,从而获得了高的编程速度和注入效率,降低了工作电压.并对SCDI器件结构和常规器件结构进行了模拟分析,提出了改进SCDI器件性能的优化方案.     

双栅MOSFET沟道侧壁绝缘柱(DP)表面势解析模型

采用抛物线近似方法求解二维泊松方程,建立了漏端沟道侧壁绝缘柱表面电势解析模型。在该解析模型下,求解了不同漏压下的表面势,并与Atlas仿真结果做对比。比较了在相同条件下,DPDG MOSFET与DG MOSFET的沟道侧壁电势与电场分布。在不同沟道长度下,分析了DPDG MOSFET器件的阈值电压(Vth),亚阈值斜率(SS)以及漏感应势垒降低效应(DIBL),并与DG MOSFET作对比。结果表明,添加绝缘柱DP后,不仅减小了源漏端电荷分享,而且增强了栅对电荷控制,从而改善了器件的DIBL效应,并有效提高了器件的可靠性。     

High Injection Efficiency and Low-Voltage Programming in a Dopant-Segregated Schottky Barrier (DSSB) FinFET SONOS for nor-type Flash Memory

A dopant-segregated Schottky barrier (DSSB) FinFET silicon–oxide–nitride–oxide–silicon (SONOS) for nor-type Flash memory is successfully demonstrated. Compared with a conventional FinFET SONOS device, the DSSB FinFET SONOS device exhibits high-speed programming at low voltage. The sharp dopant-segregated Schottky contact at the source side can generate hot electrons, and it can be used to provide high injection efficiency at low voltage without any constraint on the choice of the proper gate and drain voltage. The DSSB FinFET SONOS device is therefore a promising candidate for nor-type Flash memory with high-speed and low-power programming.      

A novel modified charge pumping method for trapped charge characterization in nanometer-scale devices

A new modified method based on the charge pumping technique is proposed and adopted to extract the lateral profiles of oxide charges in an advanced MOSFET.A 0.12μm SONOS device with 50 nm threshold voltage peak is designed and utilized to demonstrate the proposed method.The trapped charge distribution with a narrow peak can be precisely characterized with this method,which shows good consistency with the measured threshold voltage.     

Analysis of Trapped Charges in Dopant-Segregated Schottky Barrier-Embedded FinFET SONOS Devices

The aim of this letter is to analyze the spatial distribution of trapped charges in the type of dopant-segregated Schottky barrier (DSSB)-embedded FinFET SONOS devices used in NAND-type flash memory. Due to localized programming by carrier injection with extra kinetic energy, the spatial distribution of electrons trapped in an O/N/O layer of a DSSB SONOS device after a short time of programming differs from that in an O/N/O layer of a conventional SONOS device, which results in the degradation of subthreshold slope (SS). Note that the degraded SS recovers as the program time increases. The measured and simulated data confirm that the high speed of the programming is due largely to the localized trapped charges injected from DSSB source/drain junctions.     

Study of Warm-Electron Injection in Double-Gate SONOS by Full-Band Monte Carlo Simulation

In this letter, we investigate warm-electron injection in a double-gate SONOS memory by means of 2-D full-band Monte Carlo simulations of the Boltzmann transport equation. Electrons are accelerated in the channel by a drain-to-source voltage $V_{rm DS}$ smaller than 3 V, so that programming occurs via electrons tunneling through a potential barrier whose height has been effectively reduced by the accumulated kinetic energy. Particle energy distribution at the semiconductor/oxide interface is studied for different bias conditions and different positions along the channel. The gate current is calculated with a continuum-based postprocessing method as a function of the particle distribution obtained from Monte Carlo simulation. Simulation results show that the gate current increases by several orders of magnitude with increasing drain bias, and warm-electron injection can be an interesting option for programming when short-channel effects prohibit the application of larger drain bias.      

Highly Reliable Multilevel and 2-bit/cell Operation of Wrapped Select Gate (WSG) SONOS Memory

In this letter, high-performance and reliable wrapped select gate (WSG) polysilicon-oxide-nitride-oxide-silicon (SONOS) memory cells with multilevel and 2-bit/cell operation have been successfully demonstrated. The multilevel storage is easily obtained with fast program/erase speed (10 mus/5 ms) and low programming current (3.5 muA) for our WSG SONOS by a source-side injection. Besides the excellent reliability properties of our multilevel WSG-SONOS memory including unconsidered gate and drain disturbance, long charge retention (>150degC) and good endurance (>10⁴) are also presented. This novel WSG-SONOS memory with a multilevel and 2-bit/cell operation can be used in future high-density and high-performance memory application     

Scaling of multidielectric nonvolatile SONOS memory structures

Present-day low-power, portable lap-top computers and consumer products require non-volatile semiconductor memory (NVSM) operating at 5 V with a trend towards reducing this level to 3.3 V. The SONOS technology, an acronym for the polySilicon-blocking Oxide-Nitride-tunnel Oxide-Silicon structure used in capacitors and transistors, shows promise as a technology for present and future low voltage NVSM applications. The nitride layer in the dielectric sandwich permits the storage of charge resulting in adjustable threshold voltages. This paper examines the physics and characterization of scaled SONOS NVSM transistors in relation to reducing the programming voltage. We develop a model for the transient characteristics of the SONOS NVSM transistor with: (1) a simple closed-form solution valid for short programming times; and (2) a numerical solution covering the entire range of programming times. The simple closed-form solution clearly illustrates the dependence of the turn-on time and erase/white slope on the dielectric thicknesses, initial stored charge in the nitride, and programming voltage. In particular, we have examined: (1) decreasing the tunnel oxide thickness; and (2) scaling the blocking oxide thickness. By properly scaling the dielectric films (11 Å tunnel oxide, 50 Å nitride, 40 Å blocking oxide), a ±8 V programmable SONOS device has been obtained with a 50 μs write time and a 100 μs erase time for a 3 V memory window, and a ±5 V programmable device with a 100 ms erase and write time for a 1.5 V memory window.     

Positive oxide charge-enhanced read disturb in a localized trapping storage flash memory cell

Read disturb-induced erase-state threshold voltage instability in a localized trapping storage Flash memory cell with a poly-silicon-oxide-nitride-oxide-silicon (SONOS) structure is investigated and reported. Our results show that positive trapped charge in bottom oxide generated during program/erase (P/E) cycles play a major role. Both gate voltage and drain voltage will accelerate the threshold voltage (V/sub t/) drift. Hot-carrier caused disturb effect is more severe in a shorter gate length device at low temperature. A model of positive charge-assisted electron tunneling into a trapping nitride is proposed. Influence of channel doping on the V/sub t/ drift is studied. As the cell is in an "unbiased" storage mode, tunnel detrapping of positive oxide charges is responsible for the threshold voltage shift, which is insensitive to temperature.     

High performance SONOS memory cells free of drain turn-on andover-erase: compatibility issue with current flash technology

Nonvolatile SONOS memory cells, fabricated by standard flash EEPROM technology are characterized, in comparison with floating gate memory devices. Its programming speed is comparable with the state-of-the-art flash EEPROM cells, while the erase speed is faster and over-erase-free. The SONOS cells do not suffer from the drain turn-on effect, making it is possible to perform parallel multi bit-line programming and to achieve tighter distributions of programmed and erased threshold voltages. These features render SONOS cells attractive for direct utilization in existing flash EEPROM technology with its forward reading scheme     

Temperature effect on read current in a two-bit nitride-based trapping Storage Flash EEPROM cell

The temperature effect on the read current of a two-bit nitride-storage Flash memory cell is investigated. In contrast to a conventional silicon-oxide-nitride-oxide (SONOS) cell with uniform Fowler-Nordheim (FN) programming, a significant high-V/sub T/ state read current increase, which results in the read window narrowing at high temperature, is observed in a channel hot electron (CHE) programmed cell. The increment of high-V/sub T/ state leakage current shows a positive correlation with program/erase threshold voltage window. Since the temperature effect is very sensitive to a locally trapped charge profile, a two-dimensional simulation with a step charge profile is employed to characterize the relationship between current increment and both charge width and charge density.     

一种采用带-带隧穿热电子注入编程的新型快闪存贮器

提出一种采用带-带隧穿热电子注入编程的新型快闪存贮器结构,在便携式低功耗的code闪存中有着广泛的应用前景.该结构采用带-带隧穿热电子注入 (BBHE)进行"写"编程,采用源极Fowler-Nordheim隧穿机制进行擦除.研究显示控制栅编程电压为8V,漏极漏电流只有3μA/μm左右,注入系数为4×10-4,编程速度可达16μs,0.8μm存贮管的读电流可达60μA/μm.该新型结构具有高编程速度、低编程电压、低功耗、大读电流和高访问速度等优点.