PDSOI体源连接环形栅nMOS特性研究

提出了一种基于部分耗尽绝缘体上硅的体源连接环形栅nMOS器件,并讨论了相应的工艺技术和工作机理。采用体源连接环形栅器件结构,有效地抑制了浮体环形栅器件中存在的浮体效应和寄生双极晶体管效应,使器件性能得到很大的提高。消除了浮体环形栅器件的反常亚阈值斜率和Kink效应,DIBL从120.7mV/V降低到3.45mV/V,关态击穿电压从4.8V提高到12.1V。最后指出,体源连接环形栅器件非常适合于抗辐照加固等应用领域。     

提高SOI器件和电路性能的研究

在分析SOI器件的浮体效应、击穿特性、背栅阈值、边缘漏电、ESD及抗辐照特性的基础上,提出了提高SOI器件和电路性能的技术途径.体接触是防止浮体效应的最好方法;正沟道和背沟道的BF2/B离子注入可以分别满足阈值和防止背栅开启的需要;SOI器件栅电极的选取严重影响器件的性能;源区的浅结有助于减小寄生npn双极晶体管的电流增益;而自对准硅化物技术为SOI器件优良特性的展现发挥了重要作用.研究发现,采用综合加固技术的nMOS器件,抗总剂量的水平可达1×106rad(Si).     

提高SOI器件和电路性能的研究

在分析SOI器件的浮体效应、击穿特性、背栅阈值、边缘漏电、ESD及抗辐照特性的基础上,提出了提高SOI器件和电路性能的技术途径.体接触是防止浮体效应的最好方法;正沟道和背沟道的BF2/B离子注入可以分别满足阈值和防止背栅开启的需要;SOI器件栅电极的选取严重影响器件的性能;源区的浅结有助于减小寄生npn双极晶体管的电流增益;而自对准硅化物技术为SOI器件优良特性的展现发挥了重要作用.研究发现,采用综合加固技术的nMOS器件,抗总剂量的水平可达1×106rad(Si).     

提高SOI器件和电路性能的研究

在分析SOI器件的浮体效应、击穿特性、背栅阈值、边缘漏电、ESD及抗辐照特性的基础上，提出了提高SOI器件和电路性能的技术途径. 体接触是防止浮体效应的最好方法；正沟道和背沟道的BF2/B离子注入可以分别满足阈值和防止背栅开启的需要；SOI器件栅电极的选取严重影响器件的性能； 源区的浅结有助于减小寄生npn双极晶体管的电流增益；而自对准硅化物技术为SOI器件优良特性的展现发挥了重要作用. 研究发现，采用综合加固技术的nMOS器件，抗总剂量的水平可达1E6rad(Si).     

PDSOI nMOSFETs关态击穿特性

分别采用不同的背栅沟道注入剂量制成了部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件.对这些器件的关态击穿特性进行了研究.当背栅沟道注入剂量从1.0×1013增加到1.3×1013cm-2,浮体n型沟道器件关态击穿电压由5.2升高到6.7V,而H型栅体接触n型沟道器件关态击穿电压从11.9降低到9V.通过测量寄生双极晶体管静态增益和漏体pn结击穿电压,对部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件的击穿特性进行了定性解释和分析.     

PDSOI nMOSFETs关态击穿特性

分别采用不同的背栅沟道注入剂量制成了部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件.对这些器件的关态击穿特性进行了研究.当背栅沟道注入剂量从1.0×1013增加到1.3×1013cm-2,浮体n型沟道器件关态击穿电压由5.2升高到6.7V,而H型栅体接触n型沟道器件关态击穿电压从11.9降低到9V.通过测量寄生双极晶体管静态增益和漏体pn结击穿电压,对部分耗尽绝缘体上硅浮体和H型栅体接触n型沟道器件的击穿特性进行了定性解释和分析.     

PD SOI MOSFET低频噪声研究进展

随着器件尺寸的不断减小,PD SOI器件的低频噪声特性对电路稳定性的影响越来越大.研究了PD SOI器件低频过冲噪声现象,分析了此类器件在发生浮体效应、栅致浮体效应以及前背栅耦合效应时低频过冲噪声的产生机理及影响因素.最后指出,可以通过添加体接触或将PD SOI器件改进为双栅结构,达到有效抑制低频过冲噪声的目的.     

源区浅结SOI MOSFET的辐照效应模拟

研究了源区浅结的不对称SOI MOSFET对浮体效应的改善,模拟了总剂量、抗单粒子事件(SEU)、瞬时辐照效应以及源区深度对抗辐照性能的影响.这种结构器件的背沟道抗总剂量能力比传统器件有显著提高,并且随着源区深度的减小,抗总剂量辐照的能力不断加强.体接触不对称结构的抗SEU和瞬时辐照能力优于无体接触结构和传统结构器件,这与体接触对浮体效应的抑制和寄生npn双极晶体管电流增益的下降有关.     

源区浅结SOI MOSFET的辐照效应模拟

研究了源区浅结的不对称SOIMOSFET对浮体效应的改善 ,模拟了总剂量、抗单粒子事件 (SEU)、瞬时辐照效应以及源区深度对抗辐照性能的影响 .这种结构器件的背沟道抗总剂量能力比传统器件有显著提高 ,并且随着源区深度的减小 ,抗总剂量辐照的能力不断加强 .体接触不对称结构的抗SEU和瞬时辐照能力优于无体接触结构和传统结构器件 ,这与体接触对浮体效应的抑制和寄生npn双极晶体管电流增益的下降有关     

0.8 μm PDSOI CMOS器件和环振电路研究

研究了0.8μm部分耗尽绝缘体上硅(PDSOI)CMOS器件和电路,开发出成套的0.8μmPDSOI CMOS工艺.经过工艺投片,获得了性能良好的器件和电路.其中,当工作电压为5 V时,基于浮体SOI CMOS技术的0.8μm 101级环振单级延时为49.5 ps;基于H型栅体引出SOI CMOS技术的0.8μm 101级环振单级延时为158 ps.同时,对PDSOI CMOS器件的特性,如浮体效应、背栅特性、反常亚阈值斜率、击穿特性和输出电导变化等进行了讨论.     

Influence of Floating Body Effect on Radiation Hardness of PD SOI nMOSFETs

H-gate and closed-gate PD SOI nMOSFETs are fabricated on SIMOX substrate,and the influence of floating body effect on the radiation hardness is studied.All the subthreshold characteristics of the devices do not change much after radiation of the total dose of 1e6rad(Si).The back gate threshold voltage shift of closed-gate is about 33% less than that of Hgate device.The reason should be that the body potential of the closed-gate device is raised due to impact ionization,and an electric field is produced across the BOX.The floating body effect can improve the radiation hardness of the back gate transistor.     

辐照对SOI NMOS寄生双极晶体管的影响。

在埋氧化层厚度不同的SIMOX衬底上制备了H型栅结构器件。经过总剂量辐照后,器件的正栅亚阈值特性无明显变化,背栅亚阈值特性发生平移,但均未发生漏电,说明其抗辐照性能超过1E6rad(Si)。辐照后器件的寄生双极晶体管增益有所增大,并且与背栅阈值电压的变化趋势相似,可能是由于埋氧化层中的正电荷积累使体区电位升高,提高了发射极的发射效率。     

Direct tunneling-induced floating-body effect in 90-nm pseudo-kink-free PD SOI pMOSFETs with DTMOS-like behavior and low input power consumption

This paper reports the investigation of the direct tunneling-induced floating-body effect in 90-nm H-gate floating body partially depleted (PD) silicon-on-insulator (SOI) pMOSFETs with dynamic-threshold MOS (DTMOS)-like behavior and low input power consumption. Based on this paper, with the decrease of the gate-oxide thickness, the direct-tunneling current will dominate the floating body potential of H-gate PD SOI pMOSFETs, which makes the floating body potential highly gate voltage dependent like DTMOS behavior with a larger drain current. However, the input power consumption is still kept lower. Simultaneously, the highly gate voltage dependent direct-tunneling current will reduce the influence of the impact ionization current on the neutral region with a higher kink onset-voltage. It contributes to the pseudo-kink-free phenomenon in 90-nm H-gate floating body PD SOI pMOSFETs.     

边缘注入对H型栅SOI pMOSFETs亚阈值泄漏电流的影响

就不同边缘注入剂量对H型栅SOI pMOSFETs亚阈值泄漏电流的影响进行了研究。实验结果表明不足的边缘注入将会产生边缘背栅寄生晶体管,并且在高的背栅压下会产生明显的泄漏电流。分析表明尽管H型栅结构的器件在源和漏之间没有直接的边缘泄漏通路,但是在有源扩展区部分,由于LOCOS技术引起的硅膜减薄和剂量损失仍就促使了边缘背栅阈值电压的降低。     

Effects of gate structures on the RF performance in PD SOI MOSFETs

The radio-frequency (RF) performance of PD silicon-on-insulator metal oxide semiconductor field effect transistors with T-gate and H-gate structures has been investigated. Our measurement shows that H-gate devices have larger cutoff frequency and smaller minimum noise figure than T-gate devices. This improved RF performance in H-gate devices can be explained mainly by the enhancement of transconductance resulting from the gate extension induced inversion charges and the low gate resistance. We conclude that the H-gate structure is superior to the T-gate structure for the design of the low-noise amplifier (LNA).     

Gate tunneling leakage current behavior of 40 nm PD SOI NMOS device considering the floating body effect

This paper reports an analysis of floating body effect related gate tunneling leakage current behavior of the 40 nm PD SOI NMOS device using bipolar/MOS equivalent circuit approach. As confirmed by the experimentally measured data, the bipolar/MOS equivalent circuit approach could predict the gate tunneling leakage current behavior, which is strongly affected by the parasitic bipolar device in the floating body as observed from the perpendicular electric field along the path of the U-shaped edges of the polysilicon gate.     

一种抗总剂量辐照的新型PD SOI器件

提出了一种具有叠层埋氧层的新栅型绝缘体上硅(SOI)器件.针对SOI器件的抗总电离剂量(TID)加固方案,对绝缘埋氧层(BOX)采用了叠层埋氧方案,对浅沟槽隔离(STI)层采用了特殊S栅方案.利用Sentaurus TCAD软件,采用Insulator Fixed Charge模型设置固定电荷密度,基于0.18 μm ...     

Status and Trends in Advanced SOI Devices and Materials

A review of recently explored effects in advanced SOI devices and materials is given. The effects of key device parameters on the electrical and thermal floating body effects are shown for various device architectures.Recent advances in the understanding of the sensitivity of electron and hole transport to the tensile or compressive uniaxial and biaxial strains in thin film SOI are presented. The performance and physical mechanisms are also addressed in multi-gate Si, SiGe and Ge MOSFETs. New hot carrier phenomena are discussed. The effects of gate misalignment or underlap,as well as the use of the back gate for charge storage in double-gate nanodevices and of capacitorless DRAM are also outlined.