UV nanoimprint using flexible polymer template and substrate

Nano to micro-sized patterns were formed on a flexible polymer substrate using a flexible UV imprint stamp. A 6 in. diameter flexible UV nanoimprint template was fabricated using PVC hot embossing and DLC coating. Using the UV nanoimprint process with the DLC coated PVC template, nano to micro-sized patterns were clearly formed on the flexible PET substrate without a residual layer, due to the antistiction properties and high mechanical hardness of the DLC coating. By depositing a Cr layer on the imprinted resist pattern and lifting it off, Cr metal patterns were fabricated on the PET substrate.     

Replication of high ordered nano-sphere array by nanoimprint lithography

High ordered nano-sphere array patterns on Si substrate were fabricated using nanoimprint lithography. First, using hot embossing method, poly vinyl chloride (PVC) based polymer replica template was duplicated from original high ordered nano-sphere array patterns, which was fabricated by evaporation method. The monolayer transferring condition can be achieved by varying hot embossing pressure. Then, through UV nanoimprint lithography with the replicated polymer template, imprinted patterns, which has high ordered nano-sphere array patterns, was successfully fabricated on Si and flexible PET substrate.     

UV nanoimprint lithography of sub-100 nm nanostructures using a novel UV curable epoxy siloxane polymer

We reported the replication of sub-100 nm nanostructures by an ultraviolet (UV) nanoimprint lithography (NIL) technique. We used a novel UV curable epoxy siloxane polymer as the NIL resist to achieve features as small as 50 nm. The polymeric soft molds for the NIL were fabricated by casting toluene diluted poly(dimethyl-siloxane) (PDMS) on the hydrogensilsesquioxane (HSQ) hard mold. The NIL results were characterized by using a scanning electron microscope and an atomic force microscope. Our results illustrate that, with the epoxy siloxane resist, the 50 nm HSQ features on the hard mold can be successfully replicated using PDMS soft molds.     

A photo-polymerization resist for UV nanoimprint lithography

A novel liquid photo-polymerization resist was prepared for nanoimprint lithography on transparent flexible plastic substrates. The resist is a mixture of polymethylmethacrylate (PMMA), methylmethacrylate (MMA), methacylic acid (MAA) and two photo-initiators, (2-isopropyl thioxanthone (ITX) and ethyl 4-(dimethylamino)benzoate (EDAB)). The resist can be imprinted at room temperature with a pressure of 0.25 kg/cm², and then exposed from the transparent substrate side using a broad band UV lamp to obtain nano- and micro-scale patterns. Replications of high-density line and space patterns with resolution of 150 nm were obtained on a flexible indium tin oxide/poly(ethylene terephthalate) (ITO/PET) substrate. The liquid resist has low viscosity due to the liquid monomers, and low shrinkage due to the addition of PMMA as a binder.     

Printing-induced improvements of organic thin-film transistors

To understand the observation of improved pentacene (Pn) thin-film transistor mobility in flexible printed devices, a method for performing electrical measurements of organic thin-film transistors (OTFT) during the process of transfer printing has been developed. Different sample configurations were designed to test two aspects of the printing process: (1) the formation of the source/drain contacts a Pn thin-film, and (2) the formation of the transfer printed Pn/dielectric interface. In situ measurements show that pressure-induced contacts of gold (Au) electrodes result in a factor of seven mobility improvement compared with evaporation of top Au electrodes on an otherwise identical device configuration. Annealing the laminated device up to 90 °C caused no further improvement, and heating above 90 °C degraded performance. The mobility of a transfer printed device with the rough, as-grown top surface of the Pn in contact with the dielectric was found to increase dramatically with subsequent annealing for a sample temperature up to 120 °C. This is attributed to annealing-induced structural changes in the Pn film at elevated temperatures, consistent with X-ray bulk measurements showing enhanced crystal morphology in transfer printed Pn thin-films.     

Megahertz operation of flexible low-voltage organic thin-film transistors

Bottom-gate, top-contact (inverted staggered) organic thin-film transistors with a channel length of 1 μm have been fabricated on flexible plastic substrates using the vacuum-deposited small-molecule semiconductor 2,9-didecyl-dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (C₁₀-DNTT). The transistors have an effective field-effect mobility of 1.2 cm²/V s, an on/off ratio of 10⁷, a width-normalized transconductance of 1.2 S/m (with a standard deviation of 6%), and a signal propagation delay (measured in 11-stage ring oscillators) of 420 ns per stage at a supply voltage of 3 V. To our knowledge, this is the first time that megahertz operation has been achieved in flexible organic transistors at supply voltages of less than 10 V.     

High performance tetrathienoacene-DDP based polymer thin-film transistors using a photo-patternable epoxy gate insulating layer

High performance organic thin-film transistors (OTFTs) are fabricated on an epoxy based photo-patternable organic gate insulating layer (p-OGI) using a top contact thin-film transistor configuration. This negative tone p-OGI material is composed of an epoxy type polymer resin, a polymeric epoxy cross-linker, and a sulfonium photoacid generator (PAG). Features from p-OGI can be precisely patterned down to ∼3 μm via i-line photolithography. In order to evaluate the potential of this epoxy type resin as a gate insulator, we evaluated the dielectric properties of the p-OGI and its gate insulating performance upon fabricating solution processed OTFTs using an organic semiconductor (OSC), namely tetrathienoacene-DPP copolymer (PTDPPTFT4). Results show that the PTDPPTFT4 based OTFTs with this p-OGI exhibit field-effect mobilities up to 1 cm² V⁻¹ s⁻¹, indicating the potential of high performance solution processed OTFT based on an epoxy based p-OGI/OSC system.     

Channel length variation in self-aligned,nanoimprint lithography structured OTFTs

We report on the fabrication and characterization of self-aligned organic thin-film transistors with copper gate electrodes structured by nanoimprint lithography (NIL). The process has been improved to increase the compatibility with solution processed materials for future fabrication of fully printed, NIL structured transistors. We provide detailed analysis of the influence of the channel length on the fabricated devices. The on-current, the swing and the onset voltage are studied for channel lengths between 25 μm and 800 nm. The results indicate that for the given system a channel length of 5 μm results in the best device performance regarding the on-current and the subthreshold swing. This work marks a first step towards our goal of fabricating self-aligned NIL OTFTs consisting solely of printable materials.     

Two-Step curing method for demoulding in UV nanoimprint lithography

In the UV nanoimprint lithography (UV NIL), it is obvious that the resist curing process is dependent on the UV dose, therefore three states of the resist pattern, i.e., uncuring, undercuring and full-curing may occur due to an inadequate curing control method. Also the demoulding force, which can influence the pattern transferring fidelity, is largely determined by the resist-curing degree. For acquiring high pattern transferring fidelity with small demoulding force, a new demoulding method is proposed in this paper. Through an analysis of the three different pattern transferring results, i.e. rounded-feature replication, fine replication, and scooped-feature replication, which may be induced by the different resist-curing degree and the relative demoulding force, it is found that the resist-curing degree is a critical factor which affects the pattern transferring fidelity. In addition, when the resist-curing degree is too low or too high, either the imprint mould may be stained or the microstructures on the mould can be damaged, which will adversely affect the subsequent imprints in a step-and-repeat process. A new demoulding method is presented, which consists of two UV exposures. The first UV exposure is done before demoulding to under-cure the resist pattern so that the demoulding force can be reduced while maintain a short-time pattern stability. The second UV exposure follows the demoulding to full-cure the resist so as to produce a sufficient rigidity in the pattern. It is experimentally shown that this new demoulding method leads to high pattern fidelity and a small demoulding force while minimizing the mould containments or microstructures damage on it.     

A maskless laser-write lithography processing of thin-film transistors on a hemispherical surface

We report on the design and fabrication methods for a hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) on a non-planar substrate using laser-write lithography (LWL). Level-to-level alignment with a high accuracy is demonstrated using LWL method. The fabricated a-Si:H TFT exhibits a field-effect mobility of 0.27 cm²/V s, threshold voltage of 4.9 V and on/off current ratio of ∼6 × 10⁶ in a saturation regime. The obtained results demonstrate that it is possible to fabricate the a-Si:H TFTs and complex circuitry on a curved surface, using a well-established a-Si:H TFT technology in combination with the maskless lithography, for hemispherical or non-planar sensor arrays.     

Two-step surface modification for bottom-contact structured pentacene thin-film transistors

We investigated surface treatment effects of hexamethyldisilazane (HMDS), poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS) and l-cysteine on gold source/drain electrodes in bottom-contact structured pentacene thin-film transistors (TFTs). The treatment methods include spin coating and immersing. We have also researched on two-step treatment based on the combination of each treatment methods. The highest device performance was achieved by treating gold S/D electrodes with l-cysteine first and PEDOT:PSS afterwards, showing field effect mobility up to 0.35 cm²/V·s. l-cysteine can reduce the contact resistance between metal and semiconductor layer, and PEDOT:PSS acted as a hole transporting layer while HMDS decreased the surface energy, which enlarged the grain size of pentacene on it.     

Inkjet-printed copper electrodes using photonic sintering and their application to organic thin-film transistors

We report on copper (Cu) electrodes fabricated with inkjet-printed nanoparticle inks that are photonic sintered on a polymer dielectric layer and their application to source and drain electrodes in organic thin-film transistor (TFT). By using photonic sintering with a radiant energy density of 9 J/cm², printed Cu nanoparticle layers on a glass substrate showed very low electrical resistivity levels of 7 μΩ cm. By optimizing the sintering conditions on polymer dielectric, the pentacene-based TFT using these printed Cu electrodes showed good mobility levels of 0.13 cm²/Vs and high on/off current ratios of about 10⁶. In addition, we revealed that the crystal grain growth of pentacene near the printed Cu electrodes was inhibited by the thermal damage of polymer underlayer due to the high radiant energy density of the intense light.     

Patchable thin-film strain gauges based on pentacene transistors

We present a patchable thin-film strain gauge for which output current responds sensitively to external strain. For this work, integrated organic thin-film transistors using pentacene as an active component were fabricated on a freestanding polyurethaneacrylate film with high flexibility and adhesive properties providing patchability. The device can be easily mounted onto non-flat surfaces, and the output characteristics show a strong correlation with the structural strain of freestanding polymeric film, which allows the external strain applied to the device to be gauged. In addition, a surface shape can be detected after mounting the device onto a non-flat surface, and the thickness of a complex structure can be inversely calculated using a calibration curve. It is anticipated that these results will be applied to the development of various patchable sensors and thickness measurement systems, which can lead to further applications.     

Finite element analysis of low temperature thermal nanoimprint lithography using a viscoelastic model

Nanoimprint lithography (NIL) is an emerging technology that enables cost-effective and high-throughput nanofabrication. Nevertheless, there are some disadvantages to this method, especially for thermal NIL. A major disadvantage of thermal NIL is the thermal cycle, which requires a significant amount of processing time and limits the throughput. One method to overcome this disadvantage is to reduce the processing temperature. Accordingly, it is necessary to determine the effects on the processing parameters for thermal NIL at reduced temperatures and to optimize the parameters. This requires a clear understanding of the behavior of the polymer material during the thermal NIL process. This work focuses on a temperature range of T_g < T < T_g + 40 °C, in which the polymer displays a semi-molten state behavior; this temperature range is lower than conventionally used for thermal NIL. To understand how the processing conditions of temperature, pressure, pattern density, and initial thickness of the polymer resist are related to the quality of a nanoimprinted pattern, simulations of thin polymer films squeezing into nanocavities during thermal NIL were performed using a two-dimensional viscoelastic finite element analysis taking into account stress relaxation behaviors.     

Degradation of all-inkjet-printed organic thin-film transistors with TIPS-pentacene under processes applied in textile manufacturing

Printed electronics represent an alternative solution for the manufacturing of low-temperature and large area flexible electronics. The use of inkjet printing is showing major advantages when compared to other established printing technologies such as gravure, screen or offset printing, allowing the reduction of manufacturing costs due to its efficient material usage and the direct-writing approach without requirement of any masks. However, several technological restrictions for printed electronics can hinder its application potential, e.g. the device stability under atmospheric or even more stringent conditions. Here, we study the influence of specific mechanical, chemical, and temperature treatments usually appearing in manufacturing processes for textiles on the electrical performance of all-inkjet-printed organic thin-film transistors (OTFTs). Therefore, OTFTs where manufactured with silver electrodes, a UV curable dielectric, and 6,13-bis(triisopropylsilylethynyl) pentance (TIPS-pentacene) as the active semiconductor layer. All the layers were deposited using inkjet printing. After electrical characterization of the printed OTFTs, a simple encapsulation method was applied followed by the degradation study allowing a comparison of the electrical performance of treated and not treated OTFTs. Industrial calendering, dyeing, washing and stentering were selected as typical textile processes and treatment methods for the printed OTFTs. It is shown that the all-inkjet-printed OTFTs fabricated in this work are functional after their submission to the textiles processes but with degradation in the electrical performance, exhibiting higher degradation in the OTFTs with shorter channel lengths (L = 10 μm).     

One-pot surface modification of poly(ethylene-alt-maleic anhydride) gate insulators for low-voltage DNTT thin-film transistors

This study investigates the one-pot surface modification of poly(ethylene-alt-maleic anhydride) (PEMA) gate insulators crosslinked with 1,5-naphthalenediamine (1,5-NDA) for enhancing the device performance of low-voltage dinaphtho[2,3-b:2′,3′-f]thieno[3,2-b]thiophene (DNTT) organic thin-film transistors (OTFTs). Surface properties of the PEMA gate insulator could be easily modified by adding poly(maleic anhydride-alt-1-octadecene) (PMAO) to the coating solution. The surface energy of the gate insulator is strongly correlated with the growth of organic semiconductors and the charge carrier transport at the interface between the semiconductor and gate insulator. The results indicate that the device performance of low-voltage DNTT OTFTs can be improved by one-pot surface modification of the PEMA gate insulator.     

Silver nanowire-polymer composite electrode for high performance solution-processed thin-film transistors

Silver nanowires (AgNWs)/poly-(3,4-ethylenedioxythiophene/polystyrene sulphonate) (PEDOT:PSS) composite films as conductive electrode for OTFTs were prepared, and their optical and electrical properties were investigated. The conductive composite films used in this study afforded low sheet resistance of <140 Ω/sq and transmittance as high as 70% in the visible region. For the composite film with 0.1 wt.% of AgNWs, contact resistance as low as 2.7 × 10⁴ Ω cm was obtained, as examined by Transfer length model (TLM) analysis, and work function of the corresponding film was 5.0 eV. Furthermore, the composite films were employed as source and drain electrodes for top-gate/bottom-contact organic thin-film transistors (OTFTs) based on solution-processed 5,11-bistriethylsilylethynyl anthradithiophene (TES-ADT) as organic semiconductor, and the resulting device showed high electrical performance with carrier mobility as high as 0.21 cm²/V s.     

Submicron-meter tunneling field-effect poly-Si thin-film transistors with a thinned channel layer

Submicron-meter poly-Si tunneling-effect thin-film transistor (TFT) devices with a thinned channel layer have been investigated. With reducing the gate length to be shorter than 1 μm, the poly-Si TFT device with conventional MOSFET structure is considerably degraded. The tunneling field-effect transistor (TFET) structure can be employed to alleviate the short channel effect, thus largely suppressing the off-state leakage. However, for a poly-Si channel layer of 100 nm thickness, the TFET structure causes a small on-state current, which may not provide well sufficient driving current. By reducing the channel layer thickness to be 20 nm, the on-state current for the TFET structure can be largely increased, due to the enhanced bending of energy band for a thinned channel layer. As a result, for the TFET poly-Si TFTs at a gate bias of 5 V and a drain bias of 3 V, a 20-nm channel layer leads to an on-state current of about 1 order larger than that by a 100-nm channel layer, while still keeping an off-state leakage smaller than 0.1 pA/μm. Accordingly, the submicron-meter TFET poly-Si TFT devices with a thinned channel layer would show good feasibility for implementing high packing density of poly-Si TFT devices.     

Crosslinked polymer-mixture gate insulator for high-performance organic thin-film transistors

In this paper, we report on the fabrication of a crosslinked polymer-mixture gate insulator for high-performance organic thin-film transistors (TFTs). We used cyanoethylated pullulan (CEP) as a crosslinkable high-k polymer matrix and poly(ethylene-alt-maleic anhydride) (PEMA) as a polymeric crosslinking agent. Because PEMA has a high number of functional groups reactive to the hydroxyl groups of CEP, the use of PEMA is effective for minimizing the amount of remaining hydroxyl groups strongly related to the large current hysteresis and high off current of the organic TFTs. To investigate the potential of the CEP-PEMA mixture as a gate insulator, we fabricated 2,7-dioctyl[1]benzothieno[3,2-b][1]benzothiophene (C₈-BTBT) TFTs. The C₈-BTBT TFT with the 60 nm-thick CEP-PEMA gate insulator showed excellent TFT performance with a field-effect mobility of 1.4 cm²/V s and an on/off ratio of 2.4 × 10⁶.     

基于纳米压印技术制作的线偏振蓝光LED

提出一种准确计算LED偏振度(PR)的方法,并采用纳米压印技术制作了线偏振蓝光LED。方法考 虑了LED朗伯型发光,计算整个半平面入射光透过光栅的TM模在TE和TM模中所占百分比。详 细分析了光 栅材料、光栅周期、占空比和光栅高度等对PR的影响,结果表明,当Al金属光栅周期为150nm、占空 比为0.5和光栅高为120nm时,PR几乎为1;利用纳米压 印技术结合感应耦合等离子刻蚀技术,制作了 铝金属光栅。实际测试结果表明,将蓝光LED的偏振消光比(P ER)由1．0∶1．0大幅度提高为2.2∶1． 0。