Overview of Cu contamination during integration in a dual damascene architecture for sub-quarter micron technology

A detailed study of copper contaminating steps performed during integration of multilevel Cu metallisation in dual damascene architecture has been performed. Contamination at the wafer back and the bevel edge should make it difficult to use the same equipment for conventional technology and new copper based technology. Several barrier materials have been claimed as efficient against copper diffusion. However, during process integration, contamination issues will be faced before deposition of the barrier layers. Heavy contamination can occur either during Cu chemical mechanical polishing (CMP) or during dielectric etching and via opening on top of contacted copper lines. These residues, concentrated at the dielectric surface, could result in current leakage and shorts between interconnection lines. Several cleaning solutions to remove metal contamination are reviewed and their efficiencies are compared.     

New precursors for CVD copper metallization

A novel CVD copper process is described using two new copper CVD precursors, KI3 and KI5, for the fabrication of IC or TSV (Through Silicon Via) copper interconnects. The highly conformal CVD copper can provide seed layers for subsequent copper electroplating or can be used to directly fabricate the interconnect in one step. These new precursors are thermally stable yet chemically reactive under CVD conditions, growing copper films of exceptionally high purity at high growth rates. Their thermal stability can allow for elevated evaporation temperatures to generate the high precursor vapor pressures needed for deep penetration into high aspect ratio TSV vias. Using formic acid vapor as a reducing gas with KI5, copper films of >99.99 atomic % purity were grown at 250 °C on titanium nitride at a growth rate of > 1500 Å/min. Using tantalum nitride coated TSV type wafers, ∼ 1700 Å of highly conformal copper was grown at 225 °C into 32 μm × 5 μm trenches with good adhesion. With ruthenium barriers we were able to grow copper at 125 °C at a rate of 20 Å/min to give a continuous ∼ 300 Å copper film. In this respect, rapid low temperature CVD copper growth offers an alternative to the long cycle times associated with copper ALD which can contribute to copper agglomeration occurring.     

New plating bath for electroless copper deposition on sputtered barrier layers

A new copper plating bath for electroless deposition directly on conductive copper-diffusion barrier layers has been developed. This plating bath can be operated at temperatures between 20 and 50°C and has good stability. High temperature processing allows for increased deposition rates and decreased specific resistivity values for the deposited copper films. Electroless Cu films deposited from this bath showed a conformal step coverage in high aspect ratio trenches and, therefore, are promising as seed layers for copper electroplating. The effect of the bath composition, activation procedure and processing temperature on the plating rate and morphology of the deposited copper has been studied and is presented here.     

SiOF and SiO2 deposition in a HDP reactor: tool characterization and film analysis

A high density plasma chemical vapour deposition (HDP CVD) system based on electron cyclotron resonance (ECR) plasma excitation for deposition of inter metal dielectric (IMD) is presented. With the system deposition of SiO₂ and SiOF has been performed. The influence of pressure, Ar content in the flow, total flow, bias voltage, microwave power on gap fill capability and growth rate has been investigated. A figure of merit, the product of gap filling capability and growth rate is defined. In addition measurements of the uniformity of the composition over the wafer of the deposited SiO₂ and SiOF layers were performed. The dielectric constant of the layers was measured on SiOF films with different composition. The stability of these SiOF films was also analysed. This was done by treating the films with moisture and measuring composition before and after this treatment.     

Microstructure and reliability of copper interconnects

The effects of texture and grain structure on the electromigration lifetime of Cu interconnects are reported. Using different seed layers, (111)- and (200)-textured CVD Cu films with similar grain size distributions are obtained. The electromigration lifetime of (111) CVD Cu is about four times longer than that of (200) CVD Cu. For Damascene CVD Cu interconnects, the electromigration lifetime degrades for linewidths in the deep submicron range because the grains are confined as a result of conformal deposition in narrow trenches. In contrast, electroplated Cu has relatively larger grains in Damascene structure, resulting in longer electromigration lifetime than CVD Cu and no degradation for linewidths in the deep submicron range     

Copper/Polyimide Heterojunctions: Controlling Interfacial Structures Through an Additive‐Based,All‐Wet Chemical Process Using Ion‐Doped Precursors

Heterojunctions comprising copper thin films and polyimide underlayers are exploited as an important system for generating flexible microelectronic circuit elements. A fully additive‐based chemical method that allows metallization of polyimide films with copper by the in situ reduction of copper ions doped in surface‐modified polyimide precursors is reported. It is shown that dimethylamine borane is a good reducing agent for copper ions initially complexed with carboxylate anions in the hydrolyzed polyimide layers. This reduction allows diffusion of copper ions towards the film surface to form copper thin films, and simultaneously controls the fabrication of interfacial microstructures between the copper and underlying polyimide. The formation of copper thin films and composite layers is elucidated by glow‐discharge optical emission spectrometry depth profiling, scanning electron microscopy, and cross‐sectional transmission electron microscopy studies, and it is shown that the final microstructure at the copper/polyimide interface is dependent upon experimental variables: a larger amount of copper ions incorporated into the modified layers and a higher reduction rate result in the formation of a granular layer containing smaller copper nanoparticles near the film surface. The granular layers thus formed are found to play a critical role in achieving strong adhesion between metal thin films and the substrate, owing to the increased contact area and hence the increased work of adhesion between them. These results have important implications for realizing a novel adhesion scheme between deposited metals and underlying dielectrics based on nanoscale interlocking through metal nanoparticles.     

CoWBP capping barrier layer for sub 90 nm Cu interconnects

Electroless cobalt films have been obtained by deposition using a plating bath containing two reducing agents: dimethylamineborane (DMAB) and sodium hypophosphite. This formulation allows spontaneous activation on copper followed by auto catalytic electroless plating. CoWBP and CoBP films are proposed as diffusion barriers and encapsulation layers, for copper lines and via contacts for ULSI interconnect applications. The crystalline structure, chemical composition and oxidation states of the elements were studied, as well as the electrical resistivity, topography and morphology of the films. The film composition was characterized as a function of the solution composition; the barrier properties of the films were tested and an oxidation resistance study was conducted. The films were characterized and the results show that they can be applied as capping layers for ULSI copper metallization.     

Double-level copper interconnections using selective copper CVD

Selective copper CVD technique involving hydrogen reduction of hexafluoro acetylacetonate copper has been used to fill vias for fabricating double-level copper interconnect structure. The surface morphology of selectively deposited copper on copper substrate of the via bottom depends strongly on via opening process. A two-step via opening process consisting of an reactive ion etching of the insulating interlayer and a wet removal of the interlayer metal results in smooth copper plug formation by CVD. Double-level copper interconnect structures have been fabricated using this technique and a via resistance as low as 100 mΩ has been obtained for a 1 μ diameter via.     

Barrier layers for Cu ULSI metallization

Barrier layers are integral parts of many metal interconnect systems. In this paper we review the current status of barrier layers for copper metallization for ultra-large-scale-integration (ULSI) technology for integrated circuits (ICs) manufacturing. The role of barrier layers is reviewed and the criteria that determine the process window, i.e. the optimum barrier thickness and the deposition processes, for their manufacturing are discussed. Various deposition methods are presented: physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), electroless deposition (ELD), and atomic layer CVD (ALCVD) for barrier layers implementation. The barrier integration methods and the interaction between the barrier and the copper metallization are presented and discussed. Finally, the common inspection and metrology for barrier layer are critically reviewed.     

Trace copper measurements and electrical effects in LPE HgCdTe

Recent improvements in sputter initiated resonance ionization spectroscopy (SIRIS) have now made it possible to measure copper in HgCdTe films into the low 10¹³ cm⁻³ range. We have used this technique to show that copper is responsible for type conversion in n-type HgCdTe films. Good n-type LPE films were found to have less than 1 x 10¹⁴ cm⁻³ copper, while converted p-type samples were found to have copper concentrations approximately equal to the hole concentrations. Some compensated n-type samples with low mobilities have copper concentrations too low to account for the amount of compensation and the presence of a deep acceptor level is suggested. In order to study diffusion of copper from substrates into LPE layers, a CdTe boule was grown intentionally spiked with copper at approximately 3 x 10¹⁶ cm⁻³. Annealing HgCdTe films at 360°C was found to greatly increase the amount of copper that diffuses out of the substrates and a substrate screening technique was developed based on this phenomenon. SIRIS depth profiles showed much greater copper in HgCdTe films than in the substrates, indicating that copper is preferentially attracted to HgCdTe over Cd(Zn)Te. SIRIS spatial mapping showed that copper is concentrated in substrate tellurium inclusions 5–25 times greater than in the surrounding CdZnTe matrix.     

Processing of titanium films on silicon using a multiscanned electron beam

A multiscanned electron beam has been used to process titanium films thermally on single-crystal silicon. The redistribution of titanium and the composition of the processed films were studied by Rutherford backscattering. Oxygen contamination within the titanium is found to control the reaction rate. Processing conditions have been established which give stoichiometric TiSi2 layers and the removal of oxygen from the system. These results have been confirmed by Auger analysis and the surface texture has been examined using scanning electron microscopy.     

Large-Scale Synthesis of Graphene Films by Joule-Heating-Induced Chemical Vapor Deposition

We report large-area synthesis of few-layer graphene films by chemical vapor deposition (CVD) in a cold-wall reactor. The key feature of this method is that the catalytic metal layers on the SiO₂/Si substrates are self-heated to high growth temperature (900°C to 1000°C) by high-current Joule heating. Synthesis of high-quality graphene films, whose structural and electrical characteristics are comparable to those grown by hot-wall CVD systems, was confirmed by transmission electron microscopy images, Raman spectra, and current–voltage analysis. Optical transmittance spectra of the graphene films allowed us to estimate the number of graphene layers, which revealed that high-temperature exposure of Ni thin layers to a carbon precursor (CH₄) was critical in determining the number of graphene layers. In particular, exposure to CH₄ for 20 s produces very thin graphene films with an optical transmittance of 93%, corresponding to an average layer number of three and a sheet resistance of ~600 Ω/square.     

Bipolar transistor fabrication in low-temperature (745°C) ultra-low-pressure chemical-vapor-deposited epitaxial silicon

In this letter we report for the first time the successful fabrication of bipolar transistors in low-temperature (Tdep= 745°C) epitaxial silicon deposited by a chemical-vapor-deposition (CVD) technology. The epitaxial layers were deposited by an ultra-low-pressure CVD (U-LPCVD) technique utilizing an optimized in-situ predeposition argon sputter clean. The critical parameter during the sputter clean has been identified as the substrate bias. Bias voltages of -200 or -300 V create dislocations that form emitter-collector shunts during the bipolar transistor fabrication process; a bias voltage of -100 V, however, permits the deposition of essentially defect-free (<10 dislocations cm^-2by defect etching) epitaxial films suitable for bipolar transistor fabrication.     

Metal–Organic chemical vapour deposition (mocvd) growth utilising cu(acac)2 (acac  pentane-3, 5-dionato) as a source for copper-containing materials: Influence of carrier gas on surface morphology

The unsubstituted bis-β-diketonato complex of copper, Cu(acac)₂ (acac ? pentane-3, 5-dionato), has been used to deposit both elemental copper and copper oxide thin films by metal–organic chemical vapour deposition (MOCVD). For all Cu(II) bis-β-diketonates, growth of oxygen-free layers requires the breakage of four copper–oxygen bonds present in the precursor. The influence of carrier gas composition on deposit morphology has been examined for six parameter sets: both hydrous and anhydrous streams, each for reducing (H₂), inert (Ar) and oxidising (O₂) environments.     

Field-dependence of the area-density of 'cold' electron emission sites on broad-area CVD diamond films

A high area density of field-induced electron emission sites has been observed on broad-area (12 mm in diameter) CVD diamond films deposited on molybdenum substrates. Furthermore, it was found that the density increased with the electric field applied to the surface of the films. These findings indicate that the CVD diamond film has to be seen as a potentially favoured candidate among electronic materials for the development of new types of cold cathode electron source.<>     

Stress development during evaporation of Cu and Ag on silicon

This work presents results of stress measurements during deposition of thin silver and copper films on 100 μm Si substrate. The stress in thin films has been determined by means of an optical system for the measurement of sample’s curvature. This system was applied in situ in a high vacuum deposition system. For Ag films the stress occurring during deposition goes from a low compressive value to tensile for thickness less than 30 nm and to compressive above this. For Cu films we observe tensile stress for thickness less 20 nm and above 50 nm. The same general trend of stress evolution with thickness is present in all cases at initial stage. There is the same growth mode for Cu and Ag because of the similar shapes of stress curves for thickness lower than 30 nm The behavior of stress evolution was explained by island nucleation and growth, island coalescence and continuous film growth. The difference in the stress evolution above 30 nm is caused by the fact that silver may be less sensitive than copper to adsorption of impurities. Adsorbed contamination inhibits compressive stress increase generated by grain boundary and defects remaining in the film.     

Copper induced synthesis of graphene using amorphous carbon

Copper is approaching its reliability limits with respect to electromigration due to very high current density as a result of continuous technology scaling. Graphene on the other hand has excellent electrical and thermal properties which can prove to be a vital candidate for improving the reliability performance of copper interconnections in ULSI. Possibility of crystallization of amorphous carbon into graphene catalyzed by copper thin film is demonstrated in this work, as evidenced by the Raman, XPS and SIMS analysis, and the number of graphene layer synthesized can be modified with the method developed. As the synthesized graphene layers are on top of the copper film whilst the amorphous carbon source is below the copper film, no contamination of the graphene layer is presence with the method developed, improving the quality and uniformity of the grown graphene layers.     

Quantifying the impact of homogeneous metal contamination usingtest structure metrology and device modeling

Deposition of metallic impurities from HF process solutions has been investigated experimentally and explained theoretically in a qualitative manner. The depositions are shown to be electrochemical in nature in that an oxidation reduction reaction results in metal ions in solution depositing on the wafer as elements with an oxidation state of 0. The theory is only qualitative in that it can only predict which metals will deposit, not how much. Experimentally, simple transmission equations can be determined which relate metallic contamination levels on Si wafer surfaces (atoms/cm²) to metal concentration in the solution (ppb). Simple test structures have been fabricated with known amounts of iron and copper contamination in the pregate oxide clean of a 1.25 μm CMOS process. Device measurements indicate device degradation in the case of copper, confirming deposition studies that copper deposits from HF solutions. Iron contaminated wafers show no contamination related device effects, in support of theoretical predictions and deposition studies indicating iron does not deposit from HF solutions. The importance and potential usefulness of test structures as homogeneous contamination monitors is illustrated through device modeling of the contamination effects observed in the test structures that can then be used to estimate the effects of such contamination on ULSI circuit performance     

Single-step selective metallization of Mg/NH3 pretreated Teflon by copper chemical vapor deposition

The surface of Teflon^®, which can be made hydrophilic by chemical treatment in a solution of solvated electrons in the presence of magnesium, can be restored by UV photochemical oxidation under oxygen. The Mg/NH₃ treated Teflon surfaces are easily metallized in a single-step process by copper CVD when (MHY)Cu(hfac) is used as precursor (hfac, hexafluoroacetylacetonate; MHY, 2-methyl-1-hexene-3-yne). The growth rate of the copper film (thickness 200–500 nm) is in the range 30–50 nm/min. The Cu films, with a resistivity of 1.9±0.2 μΩ cm, are pure, as determined by X-ray photoelectron spectroscopy. Patterned UV irradiation of the treated Teflon resulted in an identical copper pattern after CVD and, hence, selective copper deposition could be achieved on Teflon.     

Analysis of high-power devices using proton beam induced currents

Ion beam induced charge microscopy (IBIC microscopy), a new technique which utilizes a focused beam of high energy (several MeV) protons, has been used to analyse various semiconductor structures, e.g. microelectronic circuits, radiation detectors, solar cells and CVD diamond thin films [1, 2]. Here we report the first attempt to investigate high power devices with this technique. It is demonstrated that IBIC analysis allows the characterisation of layers of different doping types located several tenths of microns below the sample surface using an ion beam energy of 2 MeV. The devices investigated are high-power light-triggered thyristors.