三维堆叠封装TSV互连结构热扭耦合应力分析与优化

建立了三维硅通孔(TSV)芯片垂直堆叠封装结构有限元分析模型,对模型在热扭耦合加载下进行了仿真分析;分析了TSV材料参数与结构参数对TSV互连结构热扭耦合应力的影响;采用了响应面与模拟退火算法对在热扭耦合加载下TSV互连结构参数进行优化设计。结果表明：TSV互连结构最大热扭耦合应力应变位于铜柱与微凸点接触面外侧;微凸点材料为SAC387时,TSV互连结构热扭耦合应力最大,该应力随SiO₂层厚度的增大而增大,随铜柱直径的增大而先增大后减小,随铜柱高度的增大而减小;最优参数水平组合为铜柱直径50μm、铜柱高度85μm、SiO₂层厚度3μm,优化后的最大热扭耦合应力下降了5.3%。     

3D堆叠封装硅通孔结构的电-热-结构耦合分析

硅通孔(TSV)技术作为三维封装的关键技术,其可靠性问题受到广泛的关注。基于ANSYS平台,通过有限元方法,对3D堆叠封装的TSV模型进行了电-热-结构耦合分析,并进一步研究了不同的通孔直径、通孔高度以及介质隔离层SiO_2厚度对TSV通孔的电流密度、温度场及热应力分布的影响。结果表明:在TSV/微凸点界面的拐角处存在较大的电流密度和等效应力,容易引起TSV结构的失效;增大通孔直径、减小通孔长度可以提高TSV结构的电-热-机械可靠性;随着SiO_2层厚度的增加,通孔的最大电流密度增大而最大等效应力减小,需要综合考虑合理选择SiO_2层厚度。     

基于热-结构耦合的3D-TSV互连结构的应力应变分析

建立了3D-TSV(硅通孔)互连结构三维有限元分析模型,对该模型进行了热-结构耦合条件下的应力应变有限元分析,研究了TSV高度和直径对3D-TSV互连结构温度场分布及应力应变的影响。结果表明:随着TSV高度和直径的增大,3D-TSV叠层芯片封装整体、焊球、间隔层、芯片和TSV及微凸点处的最高温度均逐渐降低,TSV高度和直径的增加在一定程度上有利于降低封装体各部分最高温度;随着TSV高度的增加,TSV及微凸点互连结构内的应力应变呈增大趋势。     

光学表面粒子污染物散射的单层薄膜调控特性

为了降低超精密低损耗光学元件表面粒子污染物的光散射损耗,文中提出通过在光学表面沉积单层薄膜来调控表面场强分布,从而降低散射损耗的方法。理论分析了K9玻璃超光滑光学表面不同厚度单层二氧化硅（SiO₂）和单层二氧化钛（TiO₂）薄膜表面上方半径为100 nm粒子污染物所在处的电场强度,理论分析结果发现,当SiO₂薄膜厚度为137.4 nm,TiO₂薄膜厚度为12.3 nm时,表面粒子污染物所在处的电场强度最小。在此基础上分别计算了光学元件表面沉积厚度为137.4 nm的单层SiO₂薄膜以及厚度为12.3 nm的单层TiO₂薄膜,表面粒子污染物的总散射损耗(S)和双向反射分布函数(BRDF),计算结果表明,在波长为632.8 nm的光垂直入射时,单层SiO₂薄膜和单层TiO₂薄膜可有效降低其表面粒子的BRDF,且可将K9玻璃表面的总散射分别降低12.40%和25.04%。实验验证了单层SiO₂薄膜对于表面粒子污染物散射降低的有效性。     

基于低温氧化的4H-SiC/SiO2界面态钝化方案

阐述4H-SiC晶圆的Si面上通过CVD淀积与低温热氧化生长的双层栅氧化物结构，在高温氮气环境下可降低4H-SiC/SiO₂界面的高密度界面缺陷。采用PECVD淀积一层均匀的SiO₂膜后，通过热氧化工艺在淀积膜与4H-SiC/SiO₂间生长一层很薄的氧化物过渡层。根据不同温区间热氧化温度形成的SiO₂膜晶型不同，改变界面中氮气退火过程中氮元素的引入，从而钝化4H-SiC/SiO₂的界面缺陷。     

不同退火氛围对TiN/HfO2/SiO2/Si结构电荷分布的影响

热退火技术是集成电路制造过程中用来改善材料性能的重要手段。系统分析了两种不同的退火条件(氨气氛围和氧气氛围)对TiN/HfO₂/SiO₂/Si结构中电荷分布的影响,给出了不同退火条件下SiO₂/Si和HfO₂/SiO₂界面的界面电荷密度、HfO₂的体电荷密度以及HfO₂/SiO₂界面的界面偶极子的数值。研究结果表明,在氨气和氧气氛围中退火会使HfO₂/SiO₂界面的界面电荷密度减小、界面偶极子增加,而SiO₂/Si界面的界面电荷密度几乎不受退火影响。最后研究了不同退火氛围对电容平带电压的影响,发现两种不同的退火条件都会导致TiN/HfO₂/SiO₂/Si电容结构平带电压的正向漂移,基于退火对其电荷分布的影响研究,此正向漂移主要来源于退火导致的HfO₂/SiO₂界面的界面偶极子的增加。     

偏压应力下SiC/SiO2界面间隙碳缺陷的结构和电学性质演变

SiC栅氧近界面碳缺陷是SiC MOSFET器件在偏压应力下可靠性劣化的主要根源。间隙碳缺陷Si2-C=O(Ci1)和O-C=C-O(Ci2)被认为是构成SiC/SiO₂界面缺陷能级的重要源头之一。基于第一性原理密度泛函理论,研究了不同外部电场对SiC/SiO₂界面处间隙碳缺陷的结构和电学性质的影响。结构键长键角计算结果表明,电场对缺陷Ci1和Ci2的结构影响较小,但施加电场后两种缺陷的形成能均减小,说明偏压应力更有助于这两种缺陷的形成。电荷态密度计算结果表明,不同大小和方向的偏压应力(电场)会改变Ci1和Ci2的缺陷能级位置。上述作用诠释了界面缺陷产生偏压应力不稳定问题的物理机制。     

多绝缘层结构Spindt阴极设计及工艺实现

介绍了以SiO₂ /Si₃N₄ /SiO₂ 为绝缘层的夹层结构Spindt阴极并探索了两种工艺实验方法。将干法和湿法腐蚀相结合实现了侧壁崎岖的绝缘层空腔。通过精确调节绝缘层干法刻蚀时间,结合N-甲基吡咯烷酮和等离子体去胶的工艺,解决了光刻胶变性难以去除的问题。在扫描电子显微镜下观察到顶层SiO₂直径3.8μm、底层SiO₂直径2μm、中间层Si₃N₄和自对准钼栅孔直径1.1μm、尖锥高度1.1μm的冷阴极结构形貌。研究表明,这种崎岖的侧壁能够在测试时阻断沿路放电,在大电压下能够缓解电弧放电现象,降低冷阴极的损坏。     

基于正交设计的硅通孔信号完整性分析

针对硅通孔(Through Silicon Via;TSV)高度、直径和绝缘层厚度三个结构参数建立了25种不同水平组合的HFSS仿真模型,获取了这25种TSV的回波损耗和插入损耗并进行了方差分析。结果表明:随信号频率升高,TSV最大表面电场强度和插入损耗减小而回波损耗增大;在置信度为99%时,TSV高度是影响回波损耗和插入损耗的显著性因素;TSV直径和绝缘层厚度对回波损耗和插入损耗影响均不显著;TSV高度对回波损耗和插入损耗影响最大,其次是TSV直径,最后是绝缘层厚度。     

45 nm芯片铜互连结构低k介质层热应力分析

采用铜互连工艺的先进芯片在封装过程中,铜互连结构中比较脆弱的低介电常数(k)介质层,容易因受到较高的热机械应力而发生失效破坏,出现芯片封装交互作用(CPI)影响问题.采用有限元子模型的方法,整体模型中引入等效层简化微小结构,对45 nm工艺芯片进行三维热应力分析.用该方法研究了芯片在倒装回流焊过程中,聚酰亚胺(PI)开口、铜柱直径、焊料高度和Ni层厚度对芯片Cu/低κ互连结构低κ介质层应力的影响.分析结果显示,互连结构中间层中低κ介质受到的应力较大,易出现失效,与报道的实验结果一致;上述四个因素对芯片低κ介质中应力影响程度的排序为:焊料高度＞PI开口＞铜柱直径＞Ni层厚度.     

Synthesis of a new manufacturable high-quality graded gate oxidefor sub-0.2 μm technologies

Graded gate oxide process involves a two-step synthesis of growing an oxide at a temperature above the viscoelastic temperature (T_VE ) onto a pregrown low temperature thermally grown SiO₂ layer to form a composite graded SiO₂ structure. The cooling rate is carefully modulated near T_VE~925°C to enhance growth induced stress relaxation. The pregrown SiO₂ layer provides grading and is a sink for stress accommodation for the final high temperature SiO₂ forming the interface. Both grading and modulated cooling generate a strain-free and planar Si/SiO₂ interface. Such an interface delivers significant enhancement in all aspects of device reliability and performance. These oxides are of very high-quality, robust, and manufacturable with a process capability index, C_pk>1.5. Graded gate oxide is already in the primary path of our 0.16 μm and 0.12 μm technologies     

Dielectric deposition process for Cu/SiO2 integration in a dual damascene interconnection architecture

A challenge to integrate Cu in device interconnections is to avoid Cu diffusion into silicon active zone that could seriously damage device performance, and into interlevel dielectric that could induce shorts or degrade dielectric performance. This paper relates the integration of Cu-CVD with SiO₂. Structures studied are SiO₂ deposited on Cu-CVD, and SiO₂/SiN/Cu structure: a thin SiN layer is deposited on Cu before SiO₂ to act as diffusion barrier and as an etch stop during the interconnect structure patterning. Both SiO₂ and SiN dielectric processes are made in plasma-enhanced chemical vapor deposition processes, from SiH₄ precursor with addition of, respectively, N₂O or NH₃. Cu contamination is shown to occur during the dielectric deposition onto Cu, and is enhanced by the fluorine presence in the deposition chamber. Deposition processes were evaluated in order to lower Cu contamination in the dielectric bulk. On an other hand, a noticeable degradation in Cu layer resistance was evidenced after dielectric deposition due to copper contamination during the dielectric deposition process. This issue can be addressed by the optimization of the dielectric deposition process.     

Low Weibull slope of breakdown distributions in high-k layers

The reliability of various Al₂O₃, ZrO₂ and Al₂O₃/ZrO₂ double layers with a physical oxide thickness from 3 nm to 15 nm and TiN gate electrodes was studied by measuring time-to-breakdown using gate injection and constant voltage stress. The extracted Weibull slope β of the breakdown distribution is found to be below 2 and shows no obvious thickness dependence. These findings deviate from previous results on intrinsic breakdown in SiO₂, where a strong thickness dependence was explained by the percolation model. Although promising performance on devices with high-k layers as dielectric can be obtained, it is argued that gate oxide reliability is likely limited by extrinsic factors     

基于复合介质层材料的硅通孔热结构耦合分析

硅通孔(TSV)技术是三维封装的关键技术,对三维IC的可靠性起决定性作用。基于ANSYS Workbench平台,通过有限元仿真对退火阶段的TSV模型进行热结构耦合分析。比较了二氧化硅(SiO₂)介质层与苯并环丁烯(BCB)介质层在不同负载下的热应力,研究了不同填充材料、介质层厚度、通孔直径、深宽比条件下的热应力分布和热应力影响,分析了碳纳米管掺杂的苯并环丁烯(BCB-CNT)介质层的热应力。结果表明,该复合介质层能有效降低热应力,提高了三维IC的可靠性。     

InAs/GaSb Ⅱ类超晶格长波焦平面阵列台面ICP刻蚀技术研究

本文采用SiO₂/SiN作为掩膜对InAs/GaSbⅡ类超晶格红外材料进行感应耦合等离子体（ICP）刻蚀条件研究,得到InAs/GaSbⅡ类超晶格较好的刻蚀条件以提升红外探测器性能。对ICP刻蚀过程中容易出现台面侧向钻蚀以及台面底部钻蚀两种现象进行了详细研究,通过增加SiO₂膜层厚度以及减小Ar气流量,可有效减少台面侧向钻蚀;通过减小下电极射频功率（RF）,可有效消除台面底部钻蚀。采用适当厚度的SiO₂/SiN掩膜以及优化后的ICP刻蚀参数可获得光亮平整的刻蚀表面,表面粗糙度达到0.193 nm;刻蚀台面角度大于80°,刻蚀选择比大于8.5:1;采用优化后的ICP刻蚀条件制备的长波640×512焦平面器件暗电流密度降低约1个数量级,达到3×10－4 A/cm2,响应非均匀性、信噪比以及有效像元率等相关指标均有所提高,并获得了清晰的焦平面成像图。     

Charge trapping and degradation in high-permittivityTiO2 dielectric films

Suitable replacement materials for ultrathin SiO₂ in deeply scaled MOSFETs such as lattice polarizable films, which have much higher permittivities than SiO₂, have bandgaps of only 3.0 to 4.0 eV. Due to these small bandgaps, the reliability of these films as a gate insulator is a serious concern. Ramped voltage, time dependent dielectric breakdown (TDDB), and capacitance-voltage (C-V) measurements were done on 190 Å layers of TiO₂ which were deposited through the metal-organic chemical vapor deposition (MOCVD) of titanium tetrakis-isopropoxide. Measurements of the high- and low-frequency capacitance indicate that virtually no interface states are created during constant current injection stress. The increase in leakage current upon electrical stress may be due to the creation of uncharged, near interface states in the TiO₂ film near the SiO₂ interfacial layer that give rise to increased tunneling leakage     

Visible light emitting Si/SiO2 superlattices

Six-period superlattices of Si/SiO₂ have been grown at room temperature using molecular beam epitaxy. With this mature technology, the ultra-thin (1–3 nm) Si layers were grown to atomic layer precision. These layers were separated by 1 nm thick SiO₂ layers whose thickness was also well controlled by using a rate-limited oxidation process. The chemical and physical structures of the multilayers were characterized by cross-sectional TEM, X-ray diffraction, Raman spectroscopy, Auger sputter-profile, and X-ray photoelectron spectroscopy. The analysis showed that the Si layer is free of impurities and is amorphous, and that the SiO₂/Si interface is sharp (0.5 nm). Photoluminescence (PL) measurements were made at room temperature using 457.9 nm excitation. The PL peak occurred at wavelengths across the visible range for these multilayers. The peak energy position E was found to be related to the Si layer thickness d by E (eV) = 1.60+0.72d⁻² in accordance with a quantum confinement mechanism and the bulk amorphous-Si band gap.     

硅通孔尺寸与材料对热应力的影响

通过有限元分析研究了单个硅通孔及两片芯片堆叠模型的热应力。采用单个硅通孔模型证实了应力分布受填充材料(铜,钨)的影响,提出钨在热应力方面的优越性,确定了硅通孔尺寸(通孔直径、深宽比等因素)与热应力大小间的对应关系。为寻找拥有最佳热应力的材料组合,采用两片芯片堆叠的二维模型,对常用材料的组合进行了仿真分析,发现以二氧化硅为隔离层,钨为填充金属,锡为键合层的模型具有最理想的热应力特性,此外,铜、ABF以及锡的组合也表现出良好的热应力特性。     

Effect of physical stress on the degradation of thinSiO2 films under electrical stress

In this work, we demonstrate that for ultrathin MOS gate oxides, the reliability is closely related to the SiO₂/Si interfacial physical stress for constant current gate injection (V_g^- ) in the Fowler-Nordheim tunneling regime. A physical stress-enhanced bond-breaking model is proposed to explain this. The oxide breakdown mechanism is very closely related to the Si-Si bond formation from the breakage of Si-O-Si bond, and that is influenced by the physical stress in the film. The interfacial stress is generated due to the volume expansion from Si to SiO₂ during the thermal oxidation, and it is a strong function of growth conditions, such as temperature, growth rate, and growth ambient. Higher temperatures, lower oxidation rates, and higher steam concentrations allow faster stress relaxation through viscous flow. Reduced disorder at the interface results in better reliability. Fourier transform infrared spectroscopy (FTIR) technique has been used to characterize stress in thin oxide films grown by both furnace and rapid thermal process (RTP). In conjunction with the Gibbs free energy theory, this model successfully predicts the trends of time-to-breakdown (t_bd) as a function of oxide thickness and growth conditions. The trends of predicted t_bd values agree well with the experimental data from the electrical measurement