A 16-channel capacitance-to-period converter for capacitive sensor applications

An electronic system able to read out arrays of up to sixteen different capacitive type sensors is presented. The output signal of the readout is a square wave signal, with oscillation period linearly modulated by the respective sensor capacitance under measurement. Components such as charge/discharge current control unit, a multiplexing unit and a bandgap voltage reference are integrated on chip, to obtain a stable and linear readout system for multiple sensors of variable types and capacitance ranges. The ASIC was designed and fabricated in AMS 0.35???m CMOS technology and was hosted on a PCB together with a supervising microcontroller, which is programmed to produce ratiometric measurements using reference capacitances to minimise parasitic effects. Finally, a USB interface undertakes the task of communicating the results to a personal computer. Characterization of the system was performed using (a) discrete capacitances and (b) capacitive pressure sensors. The system was evaluated in a capacitance range of 10?C140?pF exhibiting high linearity (r?=?0.9954) with sensitivity of 0.062???s/pF when tested using in-house made capacitive pressure sensors.     

An advanced PNP bipolar transistor design for a low-power and very-high-performance quarter-micron CBiCMOS process

This paper describes an advanced PNP bipolar transistor which has been designed by using the mixed two-dimensional device/circuit simulation (CODECS) [1] for a low-power and very-high-performance 0.25 μm complementary BiCMOS (CBiCMOS) device. The optimized PNP structure has a 30-nm-wide emitter, a 39-nm-wide intrinsic base region, a maximum cut-off frequency of 14 GHz and a current gain of 16 (without poly-Si emitter effect). A high performance and limits in terms of delay for pull-down of 0.25 μm CBiCMOS were obtained and compared to those offered by BiCMOS and complementary metal-oxide semiconductor circuits at different power supplies and charge capacitance. An improvement of 1.5 × at 1 pF, 1.6 × at 0.6 pF and 2 × at 0.2 pF over BiCMOS has been achieved.     

C-2C digital-to-analogue converter on insulator

A new C-2C digital-to-analogue converter (DAC) has been investigated, which uses C and 2C capacitors. It is difficult to realise the C-2C DAC scheme on a silicon wafer because of the large parasitic capacitance. However, the C-2C DAC can be fabricated on glass or quartz substrates. The C-2C DACs require considerably less area and power than conventional weighted-capacitor (WC) DACs, and operate at a much higher conversion rate. Simulation results show that an 8 bit C-2C DAC can operate at a settling time of 5.3 ns for a unit capacitance of 1 pF     

An 8 bit, 100 ms/s flash ADC

An 8-bit flash ADC capable of operation at a sampling rate higher than 100 MHz with only 1.2 W of power dissipation is described. This good performance is realized using: (1) a small transistor utilizing oxide isolation and a thick field oxide process with small parasitic capacitances; (2) an optimized design for speed, accuracy, and power; and (3) a simple comparator design with small component count. Analog input capacitance of 35 pF and full-scale bandwidth of higher than 40 MHz were obtained. An error under the beat frequency test was eliminated by decoupling the master and the slave latches of the comparator.     

Capacitance to Frequency Converter Suitable for Sensor Applications Using Telemetry

Inductively powered telemetric systems are beginning to gain interest in all fields where remote sensing is needed. In such systems power consumption, miniaturization and packaging pose the greatest design problems [1]. In this paper we present a capacitance to frequency converter suitable for working with an already presented telemetric system [2]. The system uses passive telemetry to transfer power to the transponder and pressure data to a remote base unit. Such telemetric systems are becoming ever more important in the biomedical field as the interest for in vivo measurements of different biological parameters both of humans and animals is increasing.     

片上皮法级电容测试系统专用标准件的研制

研制了一套用于片上皮法级电容测试系统的电容标准件,量值低至1 pF,频率达到1 MHz。该电容标准件采用GaAs衬底,金属-绝缘层-金属(MIM)结构的电容器阵列实现,其标称值分别为1,10和100 pF。为了消除由探针系统和外界环境引入的分布电容的影响,在芯片同一单元内设计了在片开路器,电容测量准确度达到±1%。建立了在片皮法级电容测量模型,利用组建的可溯源在片定标装置对电容样片定标后,进行重复性和稳定性考核,最终研制出年稳定性小于0.4%的电容标准件一套。测量结果及标准件应用表明,研制的标准件可为片上皮法级电容测试系统进行现场整体校准。     

A hybrid NMOS/PMOS capacitor-less low-dropout regulator with fast transient response for SoC applications

In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time about 680 nsec. It can supply current from 10 µA to 100 mA consuming quiescent current of 20.5 µA and 95 µA, respectively. It supports load capacitance from 0 to 50 pF with phase margin that increases from 43° at low load (10 µA) to 74° at high load (100 mA) and power supply rejection ratio (PSRR) less than −20 dB up to 100 kHz. The proposed LDO is designed in 130 nm CMOS technology and occupies an area of 0.11 mm². Post layout simulations show better performance compared with other reported techniques.     

High-speed InGaAlAs/InAlAs multiple quantum well optical modulatorswith bandwidths in excess of 20 GHz at 1.55 μm

The modulator has a large on/off ratio, a low driving voltage (4 V), and operates in the 1.55-μm wavelength region. Small device capacitance (0.2 pF) has been obtained by using spin-coated polyimides under the bonding pads, and small stray capacitance (0.07 pF) and bonding wide inductance (0.3 nH) have been realized. The modulator requires the lowest power yet reported for a high-frequency-operation external modulator     

加速度传感器信号处理集成电路的研制

设计并制作了一种用于差分电容式加速度传感器的信号处理电路。该电路具有模拟和脉宽调制两种输出方式 ,能够将差分电容的变化通过模拟电平和输出脉冲信号的占空比表征 ,实现了对差分电容式加速度传感器信号的测量。电路中集成了自检测驱动单元。电路采用 4 μmP阱CMOS工艺制作。初步测试结果表明 :在 1～ 5 pF内 ,电路的灵敏度为 10 .7V/ pF ,可满足大多数差分电容式传感器信号处理的要求。     

P-I-N isolation for monolithic integrated circuits

A new isolation scheme is described in which the device is fabricated in an intrinsic region isolated from other regions and from theP^{+}substrate by aP-I-Nstructure. Thus the component-to-substrate capacitance and the substrate resistance are reduced by one order of magnitude or more, and the coupling or crosstalk is consequently reduced by several orders of magnitude. The fabrication process involves only conventional epitaxy and diffusion techniques. The intrinsic regions are obtained through gold compensation. Compared toP-N-junction-isolated gold-doped integrated devices, theP-I-N-isolated circuits require only one additional step-a second epitaxial deposition. Preliminary experimental data giveP-I-Ncapacitance of about 0.013 pF/mil²and breakdown voltage of 200 volts.     

基于PS021微小电容低功耗测量电路的设计

提出一种微小电容低功耗测量电路的设计方案。该电路具有功耗低、体积小、抗干扰性强、分辨力高、刷新率高的特点。阐述了测量电路的基本原理、具体实现和各模块功能,并且通过测量0~5 pF范围的动态电容验证了电路的性能。提高了微小电容的测量精度,具有良好的应用前景。     

MOSFET寄生电容对E类功率放大器影响的研究

针对Class-E功率放大器传输效率受MOSFET寄生电容的影响,提出了一种提高传输效率的方法。通过调节RLC回路中串联谐振电容的数值,提高旁路电容的数值,调节负载回路,使其超过MOSFET自身的输出寄生电容,以达到提高输出效率的目的。计算及仿真结果表明该方法在13.56 MHz下,可以将Class-E的旁路电容的值提高到120～160 pF,大大超过了IRF510的102.98 pF的寄生输出电容。最后,通过MSO3012混合信号示波器测量电路的传输效率,并对解决方案评估和改进,将Class-E的能量传输效率从改进前的37.1%提高到改进后的54.4%。据此,实现了Class-E在神经假体中数据与能量传输的应用。     

Patient isolation in multichannel bioelectric recordings by digitaltransmission through a single optical fiber

A design for patient isolation in 64-channel electrocardiogram (ECG) recordings is presented. Small dimensions of the isolated section and the use of an optical fiber as the only connection between the isolated section and the grounded section of the measurement system ensured a minimal capacitance between the patient and the environment. The consistent low-power design of the isolated section resulted in a power consumption of 210 mW, which allowed a 10 h continuous operating time of the battery-powered isolated section. The system handles 64 signals with a dynamic range of 75 dB. Analog-to-digital conversion is performed in the isolated section with a sample rate of 1 kHz/channel. The receiver interfaces to a commercially available DMA board for a standard personal computer     

Microwave p-i-n diodes and switches based on 4H-SiC

The 4H-SiC p-i-n diodes were designed, fabricated, and characterized for use in microwave applications. The diodes with mesa structure diameters between 80 and 150 /spl mu/m, exhibited a blocking voltage of 1100 V, a 100-mA differential resistance of 1-2 /spl Omega/, a capacitance below 0.5 pF at a punchthrough voltage of 100 V and a carrier effective lifetime between 15-27 ns. X-band microwave switches based on 4H-SiC p-i-n diodes are demonstrated for the first time. The switches exhibited insertion loss as low as 0.7 dB, isolation up to 25 dB and were able to handle microwave power up to 2.2 kW in isolation mode and up to 0.4 kW in insertion mode.     

Interdigitated pn junction device with novel capacitance/voltage characteristic, ultralow capacitance and low punch-through voltage

The first demonstration of the recently disclosed channelling diode is reported. The structure combines important and unique features which can be used for a large variety of applications. The diode exhibits a novel capacitance/voltage characteristic; large capacitance variations (1 pF) have been achieved over a small voltage range. Operated as a PIN diode the device has an ultralow capacitance (0.05 pF) and a low punch-through voltage (2?3 V). This small capacitance is largely independent of the detector area and of the doping of the layers. These features are important for ultralow noise PINFET receiver applications.     

A coding framework for low-power address and data busses

This paper presents a source-coding framework for the design of coding schemes to reduce transition activity. These schemes are suited for high-capacitance buses where the extra power dissipation due to the encoder and decoder circuitry is offset by the power savings at the bus. In this framework, a data source (characterized in a probabilistic manner) is first passed through a decorrelating function f₁. Next, a variant of entropy coding function f₂ is employed, which reduces the transition activity. The framework is then employed to derive novel encoding schemes whereby practical forms for f₁ and f₂ are proposed. Simulation results with an encoding scheme for data buses indicate an average reduction in transition activity of 36%. This translates into a reduction in total power dissipation for bus capacitances greater than 14 pF/b in 1.2 μm CMOS technology. For a typical value for bus capacitance of 50 pF/b, there is a 36% reduction in power dissipation and eight times more power savings compared to existing schemes. Simulation results with an encoding scheme for instruction address buses indicate an average reduction in transition activity by a factor of 1.5 times over known coding schemes     

Integrated patch-clamp biosensor for high-density screening of cell conductance

The first fully integrated implementation of a patch-clamp measurement system is presented. The system was implemented in a 0.5 mum silicon-on-sapphire process. The system can record cell membrane currents up to plusmn 20 nA, with an rms noise of 5 pA at 10 kHz bandwidth. The system can compensate for the capacitance and resistance of the pipette electrode, up to 20 pF and 4 MOmega, respectively. The die size is 1150 by 700 mum. The power consumption is 3.3 mW at 3.3 V.     

A CMOS low-noise and low-power charge sampling integrated circuitfor capacitive detector/sensor interfaces

This paper describes the design and experimental results of a multichannel calibrationless charge sampling integrated circuit for capacitive detector/sensor interfaces. The integrated circuit incorporates multiple channels of sensitive charge preamplifiers, current/charge-mode amplifiers, pipelined analog storage cells, A/D converters, and static CMOS digital control circuitry. It is implemented in a 1.2 μm single-poly double-metal CMOS p-well technology. The power dissipation is 1 mW/channel. The input-referred equivalent noise charge (ENC) for a detector/sensor source capacitance of 30 pF and an integration time window of 128 ns is 1800 rms electrons. The input-referred channel-to-channel offset variation from chip to chip is only 292 rms electrons while the storage-cell-to-storage-cell offset variation is 142 rms electrons. The channel-to-channel gain variation from chip to chip is 1.6%     

A fully compensated active pull-down ECL circuit withself-adjusting driving capability

A new active pull-down emitter-coupled logic (ECL) circuit having full compensation against fluctuations in supply voltage and temperature is proposed. This circuit needs no capacitors but a feed-back circuit to adjust its pull-down capability to its load capacitance. The speed performance is compared between the active pull-down ECL circuit and the conventional ECL circuit using 0.8 μm SPICE parameters. The active pull-down ECL circuit is twice as fast as the conventional ECL circuit under the load capacitance of 0.8 pF with the same power dissipation. The relation between the power dissipation and the operating frequency is compared among the CMOS, the conventional ECL, and the active pull-down ECL circuits. The comparison adapts a new method in which the circuit parameters are optimized at each operating frequency. The SPICE simulation using this new method shows the conventional ECL circuit has a lower power dissipation than the CMOS circuit, even in the low operating frequency region of 100 MHz. The new active pull-down ECL circuit has the lowest power dissipation among the three circuits. The power dissipation of this circuit shows 47% lower than the CMOS circuit and 29% lower than the conventional ECL circuit at the operating frequency of 600 MHz and the load capacitance of 0.8 pF     

12路并行30Gb/s 0.18μm CMOS光接收前端放大器

给出了一个采用TSMC 0.18μm CMOS工艺设计并实现的12路30Gb/s并行光接收前端放大器.电路设计采用RGC结构和噪声优化技术,克服了CMOS光检测器大寄生电容造成的带宽不够的问题.测试结果表明,在2pF的寄生电容下单信道传输速率达到了2.5Gb/s,在0.8mVpp输入下得到了清晰的眼图.提出了一种同时采用p+保护环(PGR)、n+保护环(NGR)和深n阱(DNW)的并行放大器隔离结构,有效地抑制了并行放大器之间的串扰,减小了放大器之间的衬底耦合噪声.测量结果表明,这种结构与PGR和PGR+NGR相比,在1GHz时放大器之间的隔离度分别提高了29.2和8.1dB,在2GHz时放大器之间的隔离度分别提高了8.1和2.5dB.芯片采用1.8V电源供电,单路前端放大器的功耗为85mW,12路总功耗约为1W.