微加工工艺误差对THz折叠波导行波管性能影响

在太赫兹频段,折叠波导慢波结构主要采用微细加工技术完成。讨论了目前折叠波导慢波结构主要的微加工工艺,分析了主要工艺误差包括波导深度、侧壁垂直度对0.41 THz折叠波导慢波结构高频特性的影响。通过分析比较,a值对折叠波导行波管性能影响很大,需要在工艺中精确控制。在侧壁垂直度为89°范围以内,侧壁垂直度的变化对折叠波导行波管性能影响不大。通过仿真分析,确定了工艺中必须控制加工精确度的工艺步骤,这对0.41 THz折叠波导行波管的研制有非常重要的意义。     

采用UV-LIGA技术制作340 GHz折叠波导慢波结构

紫外光刻、电铸和注塑(UV-LIGA)技术是制作太赫兹真空电子器件(包括谐振腔、电子注通道和输出波导等)的重要方法。采用 UV-LIGA技术制作340 GHz折叠波导慢波结构,研究前烘、曝光量、后烘对 SU8胶模的影响,着重讨论了曝光量的影响并分析其原因,得出最佳工艺。另外,本文还对去胶进行了初步研究,获得了全铜的340 GHz的折叠波导结构。     

0.41 THz折叠波导慢波结构分析与设计

在0.14 THz,0.22 THz和0.34 THz折叠波导行波管研制的基础上,讨论了0.41 THz折叠波导行波管慢波结构设计与加工的可行性,分析研究了折叠波导慢波结构弯曲处直角弯曲与半圈弯曲、方形电子注通道与圆形电子注通道对色散特性、耦合阻抗、带宽、冷损耗和增益的影响。考虑了慢波结构中增加理想衰减器对该行波管带宽和增益的影响,得到了0.41 THz折叠波导行波管慢波结构的初步设计方案,为太赫兹折叠波导行波管的继续发展打下了一定基础。     

电子注通道形貌对折叠波导慢波结构的影响

折叠波导结构是一种极具潜力的太赫兹行波管慢波电路.分析了电子注通道形貌对折叠波导高频特性的影响,包括色散特性、耦合阻抗和衰减特性.仿真结果表明,相比于圆形电子注通道,矩形电子注通道的折叠波导结构色散要略微陡一些,损耗也要略微高一些.在中心频率处,矩形电子注通道结构的耦合阻抗比圆形电子注通道结构低0.5Ω左右.皮尔斯小信号理论表明,在中心频率处,矩形电子注通道结构和圆形电子注通道结构的增益速率分别为4.85 dB/cm和5.22 dB/cm,具有相似的3 dB带宽,约为6.3 GHz和7.2 GHz.粒子模拟表明,对于矩形和圆形电子注通道,54 mm(100个周期)的折叠波导慢波结构在220 GHz增益分别为24.42 dB和28.44 dB.     

基于SOI材料的刻蚀光栅分波器的制作工艺

研究了基于绝缘材料上的硅(SOI)材料的平面波导刻蚀光栅分波器的主要制作工艺.利用电感耦合等离子体刻蚀(ICP)技术,在SOI材料上制作了垂直度大于89°的光滑的光栅槽面.氧化抛光后刻蚀侧壁的表面均方根粗糙度(RMS)有3nm的改善,达到7.27nm(采样面积6.2μm×26μm).通过采用集成波导拐弯微镜代替弯曲波导使1×4分波器的器件尺寸仅为20mm×2.5mm.测试结果表明器件实现了分波功能.     

太赫兹折叠波导慢波结构的设计与微加工

从行波管工作的物理特性提出了一种获得折叠波导慢波结构参数的简单方法,给定工作频率和电压,能够获得折叠波导慢波结构的初始参数.设计了D波段的折叠波导结构来验证该方法,对其冷测特性如色散、耦合阻抗进行了分析.仿真结果表明,设计的折叠波导慢波结构在中心频率处具有较平缓的色散关系,在中心频率处耦合阻抗为3.5欧姆.在电子注电压为20.6 kV,电流为15 mA时,27 mm(50个周期)的折叠波导慢波结构在220 GHz具有13.5 dB的增益,3 dB带宽为11 GHz(213~224 GHz).同时讨论了折叠波导慢波结构的微加工工艺,并通过UV-LIGA工艺获得了实验样品.     

基于梳齿式电容加速度计的深硅刻蚀北大核心

梳齿式电容加速度计对梳齿的形貌有很高的要求,如需要梳齿侧壁具有良好的垂直度和粗糙度等。利用深硅刻蚀机对梳齿结构进行加工需要对刻蚀参数进行分析和调整。以SF_6和C_4F_8为刻蚀气体,设定深硅刻蚀中极板功率、腔室压力、刻蚀/钝化周期、气体流量等工艺参数,着重研究了刻蚀速率、垂直度、粗糙度、光刻胶选择比、均匀性等直接影响刻蚀形貌的几项因素,得到了宽5.3μm、深50μm的沟槽结构,且垂直度为89.5°,侧壁凸起高度为83.69 nm,而预期目标为垂直度90°±2°,侧壁凸起高度小于120 nm,故结果符合要求。最终将调整好的工艺用于刻蚀SOI片上的梳齿结构,得到了良好的形貌。     

InP微透镜的设计与制作北大核心

高速光电探测器采用芯片背面带微透镜的背入射结构,利用微透镜对光的汇聚提高芯片与光纤的耦合效率。软件模拟发现,光敏面直径为30μm的芯片采用背入射结构时,其等效光敏面直径大于50μm,并且透镜拱高为8～15μm时,能更好实现对光的汇聚。对于InP微透镜的制作,首先要制作出透镜形状的光刻胶胶型,然后通过电感耦合等离子体（ICP）刻蚀将光刻胶图形转移到InP衬底上。光刻胶坚膜温度与坚膜时间对光刻胶形成透镜形状有很大影响。通过优化条件,150℃坚膜3 min的光刻胶呈规则透镜形状,并且表面光滑无褶皱。通过调节反应离子刻蚀（RIE）功率和ICP功率找到了合适的InP刻蚀速率,调节Cl2和BCl3的体积流量比改变了InP和光刻胶的刻蚀选择比,从而制作出不同拱高的微透镜。     

基于SOI材料的刻蚀光栅分波器的制作工艺

研究了基于绝缘材料上的硅（SOI）材料的平面波导刻蚀光栅分波器的主要制作工艺．利用电感耦合等离子体刻蚀（ICP）技术，在SOI材料上制作了垂直度大于89°的光滑的光栅槽面．氧化抛光后刻蚀侧壁的表面均方根粗糙度（RMS）有3nm的改善，达到7.27nm（采样面积6.2μm×26μm）．通过采用集成波导拐弯微镜代替弯曲波导使1×4分波器的器件尺寸仅为20mm×2.5mm．测试结果表明器件实现了分波功能．     

1.03THz折叠波导慢波结构及电子光学系统研究

太赫兹真空电子器件成为未来主要的发展方向,本文对1.03 THz折叠波导慢波结构及电子光学系统进行了研究,分析了不同电子注通道形状对于折叠波导特性的影响,包括色散特性、耦合阻抗、衰减特性、功率、增益等,并且利用OPERA 3D软件设计了电子光学系统。仿真结果表明,在中心1.03 THz频率处,与矩形电子注通道折叠波导慢波结构相比,圆形电子注通道的结构色散曲线更为平缓,耦合阻抗提升6.9%,损耗降低6.8%;在10 GHz带宽内功率提升47.4%,增益提升1.2 dB,互作用长度缩短12.3%。在工作电压为17.4 kV时,阴极发射电流大于3 mA,电子注半径为0.012 mm,在均匀区永磁聚焦系统中可稳定传输。     

光刻胶回流技术

本文介绍了集成电路制作过程中,采用光刻胶回流技术,提高抗蚀能力和图形边缘整齐度,以获得硅片上的光刻图形与掩模版图形几何尺寸一致性很好的效果,达到电路参数一致性好和提高电路管芯成品率的目的。同时介绍了光刻胶回流的实验条件,以及如何掌握与控制好光刻胶回流的工艺技术要点。     

硅基片微型通孔加工技术

介绍了硅基片微型通孔的用连及在微机电系统发展中的重要性，从原理、过程、优缺点等方面详细叙述了激光打孔法、湿法刻蚀法、深度反应离子刻蚀法(DRIE）和光辅助电化学刻蚀法(PAECE)等四种硅基片微型通孔的加工方法，并对各种方法进行了比较，提出了各种方法的适用范围。     

集成电路和微电子机械系统加工过程中的光刻工艺模拟

基于3D元胞自动机方法实现了影像成形、曝光、后烘和光刻胶刻蚀过程等集成电路和微电子机械系统加工过程中的光刻过程模拟模块的集成.模拟结果与已有实验结果一致,表明基于3D元胞自动机方法的后烘和光刻胶刻蚀模拟模块的有效性,这对于实现集成电路和微电子机械系统的器件级的工艺模拟具有一定的实用性.     

MOEMS chip-level optical fiber interconnect

A package design, fabrication process, and assembly process to hermetically seal the microstructure area of a microoptoelectromechanical system (MOEMS) at the chip level is presented and evaluated. The packaged chip is fabricated using the Bosch deep reactive ion etching (DRIE) process on silicon on insulator (SOI) substrates. The packaging structures are formed during the batch fabrication of the MOEMS device. A hermetic seal is formed via an indium solder ring around the perimeter of the MOEMS chip that span channels etched in the silicon for optical fibers. The seal is made between the device chip, metallized optical fibers, and a cap chip with a fluxless soldering process. The integrity of the package is evaluated through die shear, fiber pull, and highly accelerated life testing (HALT).     

Photolithography Process Simulation for Integrated Circuitsand Microelectromechanical System Fabrication

基于3D元胞自动机方法实现了影像成形、曝光、后烘和光刻胶刻蚀过程等集成电路和微电子机械系统加工过程中的光刻过程模拟模块的集成. 模拟结果与已有实验结果一致，表明基于3D元胞自动机方法的后烘和光刻胶刻蚀模拟模块的有效性，这对于实现集成电路和微电子机械系统的器件级的工艺模拟具有一定的实用性.     

用于3D封装的带TSV的超薄芯片新型制作方法

提出了一种应用于3D封装的带有硅通孔(TSV)的超薄芯片的制作方法。具体方法为通过刻蚀对硅晶圆打孔和局部减薄,然后进行表面微加工,最后从硅晶圆上分离出超薄芯片。利用两种不同的工艺实现了TSV的制作和硅晶圆局部减薄,一种是利用深反应离子刻蚀(DRIE)依次打孔和背面减薄,另一种是先利用KOH溶液湿法腐蚀局部减薄,再利用DRIE刻蚀打孔。通过实验优化了KOH和异丙醇(IPA)的质量分数分别为40%和10%。这种方法的优点在于制作出的超薄芯片翘曲度相较于CMP减薄的小,而且两个表面都可以进行表面微加工,使集成度提高。利用这种方法已经在实验室制作出了厚50μm的带TSV的超薄芯片,表面粗糙度达到0.02μm,并无孔洞地电镀填满TSV,然后在两面都制作了凸点,在表面进行了光刻、溅射和剥离等表面微加工工艺。实验结果证实了该方法的可行性。     

Influence of the nature of the mask on polysilicon gate patterning in high density plasmas

High density plasma etching processes of polysilicon gates on thin gate oxide (4.5 nm) have been studied for sub-quarter micron device fabrication. The influence of the mask material on the etching performance has been investigated using either a photoresist mask or an oxide hard mask. Trenching phenomena can be observed at the edges of the gates with both types of mask. When using a photoresist mask, severe defects are formed in the gate oxide near the polysilicon gate, showing that the gate oxide has been preferentially etched during the process. We show that these defects can be attributed to the trenching induced by the main etching step of the process, which is transferred into the gate oxide before the overetch starts. The transfer of the trenching effect depends strongly on the polysilicon-to-oxide selectivity which is shown to be dependent on the presence of carbon in the process chamber. When replacing the photoresist mask by an oxide hard mask the polysilicon-to-oxide selectivity can be improved by a factor of greater than three. Therefore, the use of an oxide hard mask results in a larger process window without creating undesirable defects in the active areas of the devices.     

Fabrication of Thermoelectric Devices by Applying Microsystems Technology

Microsystems technologies were applied in the fabrication of thermoelectric (TE) microconverters. Common techniques used in microelectromechanical systems (MEMS) fabrication, namely wet etching, lift-off (with SU-8 photoresist), reactive ion etching (RIE), and lithography-electroplating-molding, were compared in the fabrication process of TE microsystems based on Bi, Sb, and Te thin-film compounds. Thin films of bismuth and antimony tellurides were deposited by co-evaporation, with figures of merit comparable to those of bulk materials. Test structures were fabricated using lithography and wet etching. The etching recipe was optimized by varying the etchant dilution and composition until higher etch rates and desired material selectivity were attained. Since the etching process is applied after deposition, this process allows prior deposition of TE materials by any deposition method; thus, films with high figure of merit can be fabricated. Moreover, wet etching does not require the use of expensive equipment.     

Deep reactive ion etching for lateral field emission devices

The authors describe the design, fabrication and testing of lateral field emission diodes utilizing the deep reactive ion etch (DRIE). Devices were fabricated on silicon-on-insulator (SOI) wafers of varied thickness, by etching the device silicon in the STS DRIE system in a single mask process. After subsequent oxidation sharpening and oxide removal, diodes were tested on a probing station under vacuum. A typical diode exhibited very high currents on the order of ~100 μA at 60 V, and turn-on voltage between 35 V and 40 V. The high electron current is emitted in such a diode by multiple sharp tips vertically spaced by 450 nm along the etched sidewall due to the pulsed nature of the DRIE process     

SOI谐振式微型电场传感器的新型制作工艺研究

This paper presents a new fabrication process for the SOI-based novel miniature electric field sensor. This new process uses polyimide film to release the SiO₂ layer.Compared with the CO₂ critical point release method,it significantly improves the device surface cleanliness and shortens the process flow.The impurity on the base layer is analyzed.The problem of peak and butterfly-type contamination occurring on the base layer of the SOI wafer during the DRIE process is discussed and solved by thickening the photoresist layer and coating with polyimide film twice.This new process could fabricate MEMS sensors and actuators such as SOI-based electric field sensors,gyroscopes,and micro mirrors and can be an alternative fabrication process compared to commercial SOIMUMPS fabrication processes.