基于遗传算法的数字电路测试生成方法

本文提出了一种基于遗传算法的数字电路测试图形生成方法，首先把被测电路的门级描述转化为易于计算的非线性网络，然后用遗传算法找到网络能量函数的最优解，从而得到被测电路的测试集．这种方法对可测故障都能生成测试，能方便地产生多故障的测试图形，同时具有较好的并行性，易于在多处理机上实现．     

模拟电路故障诊断的PSpice与Matlab仿真分析研究

根据模拟电路故障诊断中的测前模拟诊断SBT法,本文采用PSpice对待测电路CUT故障进行模拟仿真,通过小波包分析和信息熵方法提取故障电路输出信号的特征向量,利用Matlab设计的神经网络算法构建故障分类器并对电路故障进行识别与诊断。仿真实验结果表明将PSpice与Matlab相结合的诊断方法能够有效地诊断模拟电路故障,为模拟电路故障诊断的教学和科研提供参考。     

Delay fault testing using partial multiple scan chains

Delay test patterns can be generated at the functional level of the circuit using a software prototype model, when the primary inputs, the primary outputs and the state variables are available only. Functional delay test can be constructed for scan and non-scan sequential circuits. Functional delay test constructed using software prototype model can detect transition faults at the structural level quite well. Therefore, we propose a new iterative functional test generation approach. The proposed approach involves a partial multiple scan chain construction using the results of functional delay test generation at a high level of abstraction. The iterativeness of the method allows finding the compromise between the test coverage, hardware overhead and test length. Furthermore, using the partial multiple scan chains requires less hardware overhead resulting in shorter test application times. The experimental results are provided for the ITC’99 benchmark circuits. Experiments showed that the obtained transition fault coverage is on average 2% higher than using full scan and commercial automatic test pattern generator for transition faults.     

Analog Fault Diagnosis Using Conic Optimization and Ellipsoidal Classifiers

This paper introduces a new fault diagnosis strategy for analog circuits based on conic optimization and ellipsoidal classifiers. Ellipsoidal classifiers are trained for efficient and accurate fault classification of the circuit under test (CUT). In the testing phase, the output of the ellipsoidal classifiers is used to isolate the actual CUT fault. The constructed classifiers exhibit high classification rate with competitive computational complexity even if the CUT has overlapping faults. Experimental results demonstrate the superior performance of the ellipsoidal classifiers in analog fault diagnosis.     

基于分数阶相关的模拟集成电路软故障诊断* Deng Yong(邓勇), Shi Yibing(师奕兵)and Zhang Wei(张伟)

针对模拟集成电路软故障诊断的难题,提出了基于分数阶相关的方法。首先,利用分数阶小波包将待测试电路(CUT)的Volterra级数进行分解,计算出分数阶相关函数。然后,用得到的分数阶相关函数构造出待测试电路的故障特征。通过对故障特征的比较,可以将待测试电路的各种软故障状态进行辨识并对故障实现定位。标准电路的仿真实验描述了这一方法并验证了该方法对模拟集成电路软故障诊断的有效性。     

Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion

Functional broadside tests were defined to address overtesting that may occur due to high peak current demands when tests for delay faults take the circuit through states that it cannot visit during functional operation (unreachable states). The fault coverage achievable by functional broadside tests is typically lower than the fault coverage achievable by (unrestricted) broadside tests. A solution to this loss in fault coverage in the form of observation point insertion is described. Observation points do not affect the state of the circuit. Thus, functional broadside tests retain their property of testing the circuit using only reachable states to avoid overtesting due to high peak current demands. However, the extra observability allows additional faults to be detected. A procedure for observation point insertion to improve the coverage of transition faults is described. Experimental results are presented to demonstrate that significant improvements in transition fault coverage by functional broadside tests is obtained.     

Bridging Faults in Pipelined Circuits

This paper analyzes the detectability of resistive bridging faults in CMOS (micro)-pipelined circuits. Logic and electrical level detection conditions are provided for functional and I _ddq testing techniques. The kind of operations and the sensitivity to dynamic fault effects of pipelined circuits make such conditions more complex than in the combinational case. In particular, it is shown that the kind of used latches has a relevant impact on fault coverage, and should be carefully accounted in test generation and fault simulation. Finally, guidelines are drawn for the extension of combinational test generation and fault simulation algorithms to the considered case.     

OBIST methodology incorporating modified sensitivity of pulses for active analogue filter components

In this paper, oscillation-based built-in self-test method is used to diagnose catastrophic and parametric faults in integrated circuits. Sallen–Key low pass filter and high pass filter circuits with different gains are used to investigate defects. Variation in seven parameters of operational amplifier (OP-AMP) like gain, input impedance, output impedance, slew rate, input bias current, input offset current, input offset voltage and catastrophic as well as parametric defects in components outside OP-AMP are introduced in the circuit and simulation results are analysed. Oscillator output signal is converted to pulses which are used to generate a signature of the circuit. The signature and pulse count changes with the type of fault present in the circuit under test (CUT). The change in oscillation frequency is observed for fault detection. Designer has flexibility to predefine tolerance band of cut-off frequency and range of pulses for which circuit should be accepted. The fault coverage depends upon the required tolerance band of the CUT. We propose a modification of sensitivity of parameter (pulses) to avoid test escape and enhance yield. Result shows that the method provides 100% fault coverage for catastrophic faults.     

Soft Fault Diagnosis in Analog Circuits Based on Bispectral Models

Aiming at the problem to locate soft faults in analog circuits, a new approach based on bispectral models is proposed. First, the Volterra kernels of the circuit under test (CUT) are calculated. Then, the Volterra kernels are used to construct bispectral models. By comparison with the fault features of the constructed models, soft faults of linear and weak nonlinear components in the analog circuit are identified and the faults are located. Simulations and experiments show the effectiveness of the proposed method in analog circuits.,     

A hierarchical test generation methodology for digital circuits

A new hierarchical modeling and test generation technique for digital circuits is presented. First, a high-level circuit model and a bus fault model are introduced—these generalize the classical gate-level circuit model and the single-stuck-line (SSL) fault model. Faults are represented by vectors allowing many faults to be implicitly tested in parallel. This is illustrated in detail for the special case of array circuits using a new high-level representation, called the modified pseudo-sequential model, which allows simultaneous test generation for faults on individual lines of a multiline bus. A test generation algorithm called VPODEM is then developed to generate tests for bus faults in high-level models of arbitrary combinational circuits. VPODEM reduces to standard PODEM if gate-level circuit and fault models are used. This method can be used to generate tests for general circuits in a hierarchical fashion, with both high- and low-level fault types, yielding 100 percent SSL fault coverage with significantly fewer test patterns and less test generation effort than conventional one-level approaches. Experimental results are presented for representative circuits to compare VPODEM to standard PODEM and to random test generation techniques, demonstrating the advantages of the proposed hierarchical approach.     

A characterization of robust test-pairs for stuck-open faults

Tests for stuck-open faults in static CMOS circuits consist of a sequence of two input vectors. Such test-pairs may be invalidated by delays in the circuit. Test-pairs that are not invalidated by delays in the circuit are known as robust test-pairs. We present a six-valued logic system Ω = {0, 1, r, f, 0h, 1h}. We show how Ω differs from a number of other logic systems that have been proposed for test generation. This logic system abstracts the important aspects of the transition behavior of the circuit, on application of an input pair, that is necessary to characterize robust test-pairs for stuck-open faults. This characterization of robust test-pairs is used to derive:

1. an algorithm for determining if a given test-pair is a robust test-pair for a given stuck-open fault or not; and
2. a simplified algorithm for computing a robust test-pair for a stuck-open fault. The resulting algorithm for computing robust tests for stuck-open faults can be implemented by minor modifications to test generation algorithms for stuck-at faults.

     

A current based self-test methodology for RF front-end circuits

This paper presents a critical step in the realization of a robust, low overhead, current-based Built-In Self-Test (BIST) scheme for RF front-end circuits. The proposed approach involves sampling the high frequency supply current drawn by the circuit under test (CUT) and using it to extract information about various performance metrics of the RF CUT. The technique has inherently high fault coverage and can handle soft faults, hard faults as well as concurrent faults because it shifts the emphasis from detecting individual faults, to quantifying all the significant performance specifications of the CUT. This work also presents the realization of an HF current monitor which is a critical component in the proposed architecture. The current monitor has then been interfaced with three standard RF front-end circuits; a Low noise amplifier, a Single Balanced Mixer and a Voltage controlled oscillator, while minimally impacting their performance. The extracted information has then been used to create a mapping between variations in CUT performance and the sensed current spectrum. The monitor circuit has been fabricated in the IBM 6 metal, RF CMOS process, with a gain of 24 db and bandwidth of 3.9 GHz.     

Ensembles of Neural Networks for Fault Diagnosis in Analog Circuits

A new neural network-based analog fault diagnosis strategy is introduced. Ensemble of neural networks is constructed and trained for efficient and accurate fault classification of the circuit under test (CUT). In the testing phase, the outputs of the individual ensemble members are combined to isolate the actual CUT fault. Prominent techniques for producing the ensemble are utilized, analyzed and compared. The created ensemble exhibit high classification accuracy even if the CUT has overlapping fault classes which cannot be isolated using a unitary neural network. Each neural classifier of the ensemble focuses on a particular region in the CUT measurement space. As a result, significantly better generalization performance is achieved by the ensemble as compared to any of its individual neural nets. Moreover, the selection of the proper architecture of the neural classifiers is simplified. Experimental results demonstrate the superior performance of the developed approach.     

Behavioral Fault Modeling and Simulation Using VHDL-AMS to Speed-Up Analog Fault Simulation

One of the main requirements for generating test patterns for analog and mixed-signal circuits is fast fault simulation. Analog fault simulation is much slower than the digital equivalent. This is due to the fact that digital circuit simulators use less complex algorithms compared with transistor-level simulators. Two of the techniques to speed up analog fault simulation are: fault dropping/collapsing, in which faults that have similar circuit responses compared with the fault-free circuit response and/or with another faulty circuit response are considered equivalent; and behavioral/macro modeling, whereby parts of the circuit are modeled at a more abstract level, therefore reducing the complexity and the simulation time. This paper discusses behavioral fault modeling to speed-up fault simulation for analog circuits.     

Analysis of Hamming count compaction scheme

Advances in VLSI technology require changes in circuit test application methods or apparatus. The use of on-chip testing, called Built-in Testing or Built-in Self-Testing (BIST), has become popular. BIST techniques compact the output response of the circuit under test (CUT). Here we discuss a time compaction method called Hamming count (H-count). H-count encompasses all syndrome detectable faults. Simulation results and theoretical analysis illustrate the overall fault-detection potential of Hamming count. The proposed method presents simple and effective compaction technique.Since BIST methods use productive chip area, a prime concern is providing the test results using the minimal amount of space. Hardware overhead reduction through counter elimination is considered for the Hamming Count compaction test. Intelligent counter selection is necessary to minimize the impact this hardware reduction has on fault detection. A method for selecting the most advantageous syndrome and input variable counter combination to utilize as a reduced H-count test is introduced. Analysis shows that the proposed method produces an optimal pairing. The paired counters have an aliasing probability which is half an order less than that of an unmodified syndrome test with exhaustive inputs. Adaptations in the counter selection method are made using a greedy strategy for choosing multiple counters to combine with the syndrome counter.This work was funded in part by Sandia National Laboratory under contract SANDIA-27-6108.     

Functional fault models for non-scan sequential circuits

The paper presents two functional fault models that are applied for functional delay test generation for non-scan synchronous sequential circuits: the pin pair state (PPS) fault model and the pin pair full state (PPFS) fault model. The PPS fault model deals with the pairs of stuck-at faults on the primary inputs and the primary outputs, as well as, with the pairs of stuck-at faults on the previous state bits and the primary outputs. The PPFS fault model encompasses the PPS model, and additionally deals with the pairs of stuck-at faults on the primary inputs and the next state bits, as well as, with the pairs of stuck-at faults on the previous state bits and the next state bits. The main factor in assessing the quality of obtained test sequences was the transition fault coverage at the gate level of the selected according to the appropriate fault model test sequences from the generated randomly ones. The experimental results demonstrate that the implementation using presented functional fault models allow selecting the test sequences from the initial test set without the loss of transition fault coverage in many cases, and the number of the selected test sequences is much lesser than that of the initial test set. This result demonstrates that the functional delay test can be generated using the presented functional delay fault models before structural synthesis of the circuit.     

Fault Models for Quantum Mechanical Switching Networks

In classical test and verification one develops a test set separating a correct circuit from a circuit containing any considered fault. Classical faults are modelled at the logical level by fault models that act on classical states. The stuck fault model, thought of as a lead connected to a power rail or to a ground, is most typically considered. A classical test set complete for the stuck fault model propagates both binary basis states, 0 and 1, through all nodes in a network and is known to detect many physical faults. A classical test set complete for the stuck fault model allows all circuit nodes to be completely tested and verifies the function of many gates. It is natural to ask if one may adapt any of the known classical methods to test quantum circuits. Of course, classical fault models do not capture all the logical failures found in quantum circuits. The first obstacle faced when using methods from classical test is developing a set of realistic quantum-logical fault models (a question which we address, but will likely remain largely open until the advent of the first quantum computer). Developing fault models to abstract the test problem away from the device level motivated our study. Several results are established. First, we describe typical modes of failure present in the physical design of quantum circuits. From this we develop fault models for quantum binary quantum circuits that enable testing at the logical level. The application of these fault models is shown by adapting the classical test set generation technique known as constructing a fault table to generate quantum test sets. A test set developed using this method will detect each of the considered faults.     

Functional versus random test generation for sequential circuits

This article presents a test generation method for sequential circuits based on their synthesis specifications as finite state machines (FSM) and provides comparison with random test generation. The finite state machines are represented by their state transition graph (STG). The test generation method is performed in two phases. The first phase is functional. It generates a test sequence which is one of the shortest input sequences going through all the transitions of the state transition graph machine. This sequence provides a high fault coverage of stuck-at faults on the synthesized circuit compared to a randomly generated test sequence. This fault coverage is very close to the ones of other sequences derived by fault-oriented test generation approaches [9], [10], although these latter sequences are much longer.The trend of the fault coverage curve for different test sequences including progressively the transitions of the test sequence defined in the first phase is similar to the one of the fault coverage curve of a random sequence but for same lengths the first curve gives larger fault coverage. Both curves grow rapidly until a given ratio of faults is detected then continue to grow very slowly exhibiting low efficiency.The second phase of the test generation method is fault-oriented. It uses a fault simulation based approach in order to compute the test sequence for the remaining faults not detected by the first phase. At the end of this phase the test sequence for all the nonredundant faults is derived and, the combinationally redundant faults and the sequentially redundant faults are distinguished.