A low power high gain gain-controlled LNAC＋mixer for GNSS receivers

A low power high gain gain-controlled LNAC+mixer for GNSS receivers is reported. The high gain LNA is realized with a current source load.Its gain-controlled ability is achieved using a programmable bias circuit. Taking advantage of the high gain LNA, a high noise figure passive mixer is adopted. With the passive mixer, low power consumption and high voltage gain of the LNACmixer are achieved. To fully investigate the performance of this circuit, comparisons between a conventional LNAC+mixer, a previous low power LNAC+mixer, and the proposed LNAC+mixer are presented. The circuit is implemented in 0.18 m mixed-signal CMOS technology. A 3.8 dB noise figure, an overall 45 dB converge gain and a 10 dB controlled gain range of the two stages are measured. The chip occupies 0.24 mm2and consumes 2 mA current under 1.8 V supply.     

一种用于超宽带接收机的CMOS可变增益低噪声放大器

本文介绍一种符合中国超宽带应用标准的工作频率范围为4.2-4.8 GHz的CMOS可变增益低噪声放大器(LNA)。文章主要描述了LNA宽带输入匹配的设计方法和低噪声性能的实现方式,提出一种3位可编程增益控制电路实现可变增益控制。该设计采用0.13-μm RF CMOS工艺流片,带有ESD引脚的芯片总面积为0.9平方毫米。使用1.2 V直流供电,芯片共消耗18 mA电流。测试结果表明,LNA最小噪声系数为2.3 dB,S(1,1)小于-9 dB,S(2,2)小于-10 dB。最大和最小功率增益分别为28.5 dB和16 dB,共设有4档可变增益,每档幅度为4 dB。同时,输入1 dB压缩点是-10 dBm,输入三阶交调为-2 dBm。     

A CMOS variable gain LNA for UWB receivers

A CMOS variable gain low noise amplifier(LNA) is presented for 4.2-4.8 GHz ultra-wideband application in accordance with Chinese standard.The design method for the wideband input matching is presented and the low noise performance of the LNA is illustrated.A three-bit digital programmable gain control circuit is exploited to achieve variable gain.The design was implemented in 0.13-μm RF CMOS process,and the die occupies an area of 0.9 mm~2 with ESD pads.Totally the circuit draws 18 mA DC current from 1.2 V DC supply,the LNA exhibits minimum noise figure of 2.3 dB,S(1,1) less than -9 dB and S(2,2) less than -10 dB.The maximum and the minimum power gains are 28.5 dB and 16 dB respectively.The tuning step of the gain is about 4 dB with four steps in all.Also the input 1 dB compression point is -10 dBm and input third order intercept point(IIP3) is -2 dBm.     

一种用于北斗导航接收机的全集成差分LNA

基于SMIC 180 nm CMOS工艺,设计了一款用于北斗导航接收机射频前端的低噪声放大器。在该低噪声放大器中,所有电感均为片上实现,提高了集成度;采用差分结构,提升了共模噪声抑制能力。LNA的输入和输出均为50 Ω标准阻抗匹配。测试结果表明,当频率为1.27 GHz时,该LNA的功率增益为15 dB,噪声系数(NF)为2.3 dB,1dB压缩点(P1dB)为－6 dBm。差分电路单路功耗为25 mW,芯片面积为1.2 mm²。     

A low-voltage ultra-wideband down-conversion mixer with improved power conversion gain

This article presents a wideband mixer using a TSMC 0.18?µm complementary metal-oxide semiconductor technology process for ultra-wideband (UWB) system applications. The measured 3-dB radio frequency (RF) bandwidth is from 3 to 8.4?GHz with an intermediate frequency of 10?MHz. The measurement results of the proposed mixer achieve 8.1?dB average power conversion gain ?5?dBm input third-order intercept point (IIP3) at 7.4?GHz and 12.4–13.3?dB double side band noise figure. The total dc power consumption of this mixer including output buffers is 3.18?mW from a 1?V supply voltage. The output current buffer consumption is about 2.26?mW with an excellent local oscillator-RF isolation of up to 40?dB at 5?GHz. The article presents a mixer topology that is greatly suitable for low-power operation in UWB system applications.     

一种应用于无线传感器网络的低电压低功耗上混频器

This paper presents an up-conversion mixer for 2.4-2.4835 GHz wireless sensor networks （WSN） in 0.18 μm RF CMOS technology. It was based on a double-balanced Gilbert cell type, with two Gilbert cells having quadrature modulation applied. Current-reuse and cross positive feedback techniques were applied in the mixer to boost conversion gain; the current source stage was removed from the mixer to improve linearity. Measured results exhibited that under a 1 V power supply, the conversion gain was 5 dB, the input referred 1 dB compression point was -11 dBm and the IIP3 was -0.75 dBm, while it only consumed 1.4 mW.     

一个应用于卫星导航接收机的低功耗可配置双频多模射频前端

本文给出了一个应用于GPS、北斗、伽利略和Glonass四种卫星导航接收机的高性能双频多模射频前端。该射频前端主要包括有可配置的低噪声放大器、宽带有源单转双电路、高线性度的混频器和带隙基准电路。详细分析了寄生电容对源极电感负反馈低噪声放大器输入匹配的影响,通过在输入端使用两个不同的LC匹配网络和输出端使用开关电容的方法使低噪声放大器可以工作在1.2GHz和1.5GHz频带。同时使用混联的有源单转双电路在较大的带宽下仍能获得较好的平衡度。另外,混频器采用MGTR技术在低功耗的条件下来获得较高的线性度,并不恶化电路的其他性能。测试结果表明：在1227.6MHz和1557.42MHz频率下,噪声系数分别为2.1dB和2.0dB,增益分别为33.9dB和33.8dB,输入1dB压缩点分别0dBm和1dBm,在1.8V电源电压下功耗为16mW。     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below-8.5 dB across the 3.1-4.7 GHz frequency range, max-imum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of-11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm2.     

Low power high gain CMOS LNA based on inverter cell and self-body bias for UWB receivers

A low-power low-noise amplifier (LNA) utilized a resistive inverter configuration feedback amplifier to achieve the broadband input matching purposes. To achieve low power consumption and high gain, the proposed LNA utilizes a current-reused technique and a splitting-load inductive peaking technique of a resistive-feedback inverter for input matching. Two wideband LNAs are implemented by TSMC 0.18 μm CMOS technology. The first LNA operates at 2–6 GHz. The minimum noise figure is 3.6 dB. The amplifier provides a maximum gain (S₂₁) of 18.5 dB while drawing 10.3 mW from a 1.5-V supply. This chip area is 1.028×0.921 mm². The second LNA operates at 3.1–10.6 GHz. By using self-forward body bias, it can reduce supply voltage as well as save bias current. The minimum noise figure is 4.8 dB. The amplifier provides a maximum gain (S₂₁) of 17.8 dB while drawing 9.67 mW from a 1.2-V supply. This chip area is 1.274×0.771 mm².     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.