A 1.8 V CMOS fourth-order Gm-C bandpass sigma-delta modulator dedicated to front-end ultrasonic receivers

A 4th order bandpass sigma-delta modulator for ultrasound applications is presented. By cascading two second-order identical Gm-C bandpass filters, a 4th-order modulator was designed with high power-efficiency, stability, tunability and programmability. The modulator is dedicated for application with intermediate frequency of 3 MHz and bandwidth of 200 kHz. Implemented in a standard 0.18 μm CMOS technology, the post-layout simulation of the modulator gives a dynamic range of 78 dB. Chip measurements are reported after successfully tuning the modulator to operate at four-time of its folded specifications. The final SNR achieves 58 dB at 0.75 MHz with 50 kHz bandwidth. The modulator consumes 2.5 mW from 1.8 V power supply. Moreover, a programming method is introduced and corresponding circuit is designed to change the central frequency of the modulator between 3 and 20 MHz for scanning different regions of the body. However the 200 kHz bandwidth limits the modulator only for Dobbler mode applications, the effective facilities of programmability are valuable property to expand this application to other wide band applications in future. Lisheng Qin received the B.Sc. degree in electrical engineering from Tianjin University, China in 1992. He was with Polystim Neurotechnologies Laboratory from 2001 to 2005 and received the M.Sc. degree in electronics engineering from Ecole Polytechnique de Montreal, Canada in 2005. He is now with Apexone Microelectronics Inc. as Analog/Mixed-Signal Design Engineer. Kamal El-Sankary received the B.Sc. degree in electrical engineering from the Lebanese University, Lebanon in 1997 and the M.Sc. degree in electronics engineering from University of Quebec in Trois Rivieres, Canada, in 2001. He is currently pursuing the Ph.D. degree in microelectronics at Ecole Polytechnique de Montreal, Canada. His research interests include analog/mixed-signal circuits design and signal processing. Mohamad Sawan received the B.Sc. degree in electrical engineering from Université Laval, Canada in 1984, the M.Sc. and Ph.D. degrees, both in electrical engineering, from Université de Sherbrooke, Canada, in 1986 and 1990 respectively, and postdoctorate training from McGill University, Canada in 1991. He joined Ecole Polytechnique de Montréal in 1991 where he is currently a Professor in Microelectronics. His scientific interests are the design and test of mixed-signal (analog, digital and RF) circuits and systems, the digital and analog signal processing, the modeling, design, integration, assembly and validation of advanced wirelessly powered and controlled monitoring and measurement techniques. These topics are oriented toward the biomedical implantable devices and telecommunications applications. Dr. Sawan is a holder of a Canadian Research Chair in Smart Medical Devices. He is leading the Microelectronics Strategic Alliance of Quebec (Regroupement stratégique en microélectronique du Québec - ReSMiQ). He is founder of the Eastern Canadian IEEE-Solid State Circuits Society Chapter, the International IEEE-NEWCAS conference, and Polystim neurotechnologies laboratory at the Ecole Polytechnique de Montreal. He is cofounder of the International Functional Electrical Stimulation Society (IFESS), and the IEEE International conference on Electronics, Circuits and Systems (ICECS). Dr. Sawan is involved in the committees of many national and international conferences and other scientific events. He published more than 300 papers in peer reviewed journals and conference proceedings and is awarded 6 patents. He is editor of the Springer Mixed-signal Letters, Distinguished Lecturer for the IEEE CAS Society, President of the biomedical circuits and systems (BioCAS) technical committee of the IEEE CAS Society, and he is representative of IEEE-CAS in the International Biotechnology council. He received the Barbara Turnbull 2003 award for spinal cord research, the Medal of Merit from Lebanon, and the Bombardier Medal from the French Association for the advancement of sciences. Dr. Sawan is Fellow of the Canadian Academy of Engineering, and Fellow of the IEEE.     

A low-power sigma-delta modulator for wireless communication receivers using adaptive biasing circuitry and cascaded comparator scheme

This paper represents the low-power signal-delta (ΣΔ) modulator for wireless communication receiver applications. The 2nd-order modulator has a single-loop structure with 11 quantization levels. An adaptive biasing scheme of the operational amplifier and cascaded comparator scheme are proposed in order to save the power consumption. The DAC with three-level references including the analog ground voltage can make the modulator be implemented with half of the input capacitances without degradation of linearity characteristics with the help of dynamic element matching technique. Peak SNR values of 74 dB and 68 dB are achieved with the input bandwidths of 615 kHz and 1.92 MHz for CDMA-2000 and WCDMA applications, respectively. The modulator is fabricated in a 0.13-μm standard digital CMOS technology and dissipates 4.3 mA for a single supply voltage of 2.8 V. Jinup Lim was born in Seoul, Korea, in 1973. He received the B.S. and the M.S. degrees in semiconductor engineering from University of Seoul, Seoul, Korea, in 1999 and 2001, respectively. From 2001 to 2002, he worked in GCT Semiconductor Inc., Seoul, Korea. He is currently working toward the Ph.D. degree in Electrical & Computer Engineering at the same university. He received the Best student paper award from IEEE SSCS/EDS Seoul Chapter in 2004 and the Samsung Best paper award third prize in ISOCC 2004. His research area is the design of high-performance discrete-time / continuous-time sigma-delta modulator circuits. Joongho Choi was born in Seoul, Korea, in 1964. He received the B.S. and the M.S. degrees in electronics engineering from Seoul National University, Seoul, Korea, in 1987 and 1989, respectively. In 1993, he received Ph.D. degree in electrical engineering from University of Southern California, CA, USA. From 1994 to 1996, he worked in IBM T. J. Watson Research Center, NY, USA. In 1996, he joined the University of Seoul, Seoul, where he is currently a professor in the Department of Electrical & Computer Engineering. His research area is the design of high-performance analog integrated circuits.     

A 0.13 μm CMOS adaptive sigma-delta modulator for triple-mode GSM/Bluetooth/UMTS applications

This paper describes the design and experimental characterization of a 0.13 μm CMOS switched-capacitor reconfigurable cascade ΣΔ modulator intended for multi-standard GSM/Bluetooth/UMTS hand-held devices. Both architectural- and circuital-level reconfiguration strategies are incorporated in the chip in order to adapt the effective resolution and the output rate to different standard specifications with optimized power dissipation. This is achieved by properly combining different reconfiguration modes that include the variation in the order of the loop filter (3rd- or 4th-order), the clock frequency (40 or 80 MHz), the internal quantization (1 or 2 bits), and the bias currents of the amplifiers. The selection of the modulator topology and the design of its building blocks are based on a top-down CAD methodology that combines simulation and statistical optimization at different levels of the modulator hierarchy. Experimental measurements show a correct operation of the prototype for the three standards, featuring dynamic ranges of 83.8/75.9/58.7 dB and peak signal-to-(noise+distortion) ratios of 78.7/71.3/53.7 dB at 400 ksps/2/8 Msps, respectively. The modulator power consumption is 23.9/24.5/44.5 mW, of which 9.7/10/24.8 mW are dissipated in the analog circuitry. The multi-mode ΣΔ prototype shows an overall performance that is competitive with the current state of the art.¹     

14-b400-ksps 2.5-mW连续时间Σ-Δ调制器

连续时间Σ-Δ调制器较之传统的开关电容Σ-Δ调制器具有更低的功耗、更小的面积,以及集成抗混叠滤波器等诸多优势。设计了一种应用于低中频GSM接收机的4阶单环单比特结构的连续时间Σ-Δ调制器。在调制器中,采用了开关电容D/A转换器,以降低时钟抖动对性能的影响。仿真结果显示,在1.8 V工作电压2、00 kHz信号带宽、0.18μm CMOS工艺条件下,采样频率21 MHz,动态范围(DR)超过90 dB,功耗不超过2.5 mW。     

一种用于微机械惯性传感器中的16位ΣΔ调制器

A fourth-order low-distortion low-pass sigma-delta （∑△） modulator is presented for micro-machined inertial sensors. The proposed single-loop single-bit feedback modulator is optimized with a feed-forward path to decrease the nonlinearities and power consumption. The IC is implemented in a standard 0.6 μm CMOS technology and operates at a sampling frequency of 3.846 MHz. The chip area is 2.12 mm^2 with 23 pads. The experimental results indicate a signal-to-noise ratio （SNR） of 100 dB and dynamic range （DR） of 103 dB at an oversampling rate （OSR） of 128 with the input signal amplitude of-3.88 dBFS at 9.8 kHz; the power consumption is 15 raW at a 5 V supply.     

A 100-MHz bandpass sigma-delta modulator with a 75-dB dynamic range for IF receivers

A fourth-order switched-capacitor bandpassΣ△modulator is presented for digital intermediatefrequency (IF) receivers.The circuit operates at a sampling frequency of 100 MHz.The transfer function of the resonator considering nonidealities of the operational amplifier is proposed so as to optimize the performance of resonators.The modulator is implemented in a 0.13-μm standard CMOS process.The measurement shows that the signal-to-noise-and-distortion ratio and dynamic range achieve 68 dB and 75 dB,respectively,over a bandwidth of 200 kHz centered at 25 MHz,and the power dissipation is 8.2 mW at a 1.2 V supply.     

A 1.8 V tri-mode ΣΔ modulator for GSM/WCDMA/WLAN wireless receiver

The next generation of cellular systems will be increasingly similar to a data communication system. Not only will it transfer voice and multimedia data, it will also be integrated with WLAN to access Internet whenever possible. Thus these cellular systems need highly integrated multi-standard receivers. The design of the A/D converter in such receivers is a big challenge. A GSM/WCDMA/WLAN tri-mode receiver is first designed on the system level. A reconfigurable ΣΔ modulator, which is suitable for GSM/WCDMA/WLAN receiver, is then proposed in this paper. According to the different signal bandwidth and Dynamic Range (DR) specifications, this ΣΔ modulator is reconfigured to achieve the required dynamic range with less power consumption. The prototype is implemented in TSMC 0.18-μm CMOS process with 1.8 V power supply. The circuit achieves signal-to-noise-and-distortion-ratio of 82 dB for GSM, 75 dB for WCDMA and 58 dB for WLAN. Ling Zhang obtained her B.S. and M.S. degrees in Automatic Control from Beijing University of Aeronautics and Astronautics, Beijing, China, in 1993 and 1996, respectively. She received the Ph.D. degree in Electrical Engineering from the Ohio State University, Columbus, OH, in 2005. She is currently with Nvidia Corporation, Santa Clara, CA. Her research interests lie in mixed-signal circuits, including multi-standard wireless receiver design, high speed sigma-delta ADC and frequency synthesizer/PLL/CDR. Hyung Joon Kim received the Master and Ph.D degree from Ohio State University, Columbus, Ohio in 1999 and 2005, respectively. Since 2004, he is with Intel Corporation, Chandler, AZ., where he is involved in various wireless receiver designs. Vinay Nadig was born in Bangalore, India in 1977. He received the M.S. degree in Electrical Engineering from The Ohio State University and is currently working towards his PhD degree there. His research interests include low power sigma delta ADCs for wireless receivers and design methodologies for complex mixed signal systems. Mohammed Ismail has over 20 years experience of R&D in the fields of analog, RF and mixed signal integrated circuits. He has held several positions in both industry and academia and has served as a corporate consultant to nearly 30 companies in the US, Europe and the far east. He is The Founding Director of the Analog VLSI Lab at Ohio State and has advised the thesis work of 39 PhD and over 75 MS students. His current interest lies in research involving digitally programmable/configurable fully integrated radios with focus on low voltage/low power first-pass solutions for 3G and 4G wireless handhelds. He publishes intensively in this area and has been awarded 11 patents. He has co-edited and co-authored several books including a text on Analog VLSI Signal and Information Processing, (McGraw Hill). His last book (2004) is entitled CMOS PLLs and VCOs for 4G Wireless, Springer. He co-founded ANACAD-Egypt (now part of Mentor Graphics, Inc.) and Spirea AB, Stockholm (now Firstpass Technologies Inc.), a developer of CMOS radio and mixed signal IPs for handheld wireless applications. Dr. Ismail has been the recipient of several awards including the US National Science Foundation Presidential Young Investigator Award, the US Semiconductor Research Corp Inventor Recognition Awards in 1992 and 1993, the Ohio State Lumley Research Award in 1992 1997 and 2002 and a Fulbright/Nokia fellowship Award in 1995. He is the founder of the International Journal of Analog Integrated Circuits and Signal Processing, Springer and serves as the Journal's Editor-In-Chief. He has served as Associate Editor for many IEEE Transactions, was on the Board of Governors of the IEEE Circuits and Systems Society and is the Founding Editor of “The Chip” a Column in The IEEE Circuits and Devices Magazine. He obtained his BS and MS degrees in Electronics and Communications from Cairo University, Egypt and the PhD degree in Electrical Engineering from the University of Manitoba, Canada. He is a Fellow of IEEE.     

改进的适用于GSM的单环过采样调制器

传统的前馈结构由于在量化器前存在复杂的加法器因而会造成性能受限。本文给出了一个改进的四阶一位过采样调制器, 它采用了简单的加法器和延时输入前馈通路,从而降低了调制器的时序需求同时实现低失真。调制器由0.35微米工艺流片,完成了92.8dB的信号噪声失真比和101dB的动态范围,信号带宽100kHz,在3.3V电源电压下,消耗8.6mW。本调制器的性能满足GSM系统的需求。     

An improved single-loop sigma-delta modulator for GSM applications

Traditional feedforward structures suffer from performance constraints caused by the complex adder before quantizer.This paper presents an improved 4th-order 1 -bit sigma-delta modulator which has a simple adder and delayed input feedforward to relax timing constraints and implement low-distortion.The modulator was fabricated in a 0.35μm CMOS process,and it achieved 92.8 dB SNDR and 101 dB DR with a signal bandwidth of 100 kHz dissipating 8.6 mW power from a 3.3-V supply.The performance satisfies the requirements of a GSM system.     

Reconfigurable terminals for mobile communication systems

Mobile phones of the future will be the access terminals to many different types of service. This will mean that they must be able to reconfigure themselves to support the differing service requirements placed upon them. At the root of this ability to reconfigure must be components and architectures that allow such flexibility, and so the key objective of the work programme on terminals within the Virtual Centre of Excellence in Mobile and Personal Communications (Mobile VCE) has been the design, definition and performance evaluation of key components and architectures for future generation reconfigurable terminals     

一种面向智能传感器的低功耗高精度sigma-delta调制器设计

设计了一款工作在1.2 V电源电压下,功耗为196μW,精度为14 bit,FOM值达202.4,应用于物联网领域的ΣΔ调制器,其OSR为64,采用四阶前馈单位量化结构,大幅度降低了系统对OTA的要求。通过Matalb SD-TOOLBOX确定系统参数,进行行为级建模确定最优值,同时对系统架构和电路模块进行低功耗分析,针对调制器各级进行适当的增益缩放。该调制器采用SMIC0.18μCMOS工艺设计,输入信号频率为3.4 k Hz,采样时钟为1.28 MHz时,调制器SNDR达到88.6 d B,达到有效位14 bit精度,处理带宽10 k Hz的要求。     

Analog signal generator for BIST of wideband IF signals bandpass sigma-delta modulator

This paper presents improvements in generation of wideband and high dynamic range analog signal for area-efficient MADBIST, especially for the on-chip testing of wireless communication IF digitizing sigma-delta modulator chip. Via increasing the order of the one-bit bandpass sigma-delta modulation algorithm up to 12 and using finite repetitious bitstream approximating scheme, it can achieve great improvements in signal bandwidth instead of purity at the cost of very little hardware overhead. Another contribution in this work is to provide the theoretical analysis of the reconstructed signal degradation due to harmonic distortion and clock jitter. Such on-chip analog stimulus generation scheme is especially fit for IF digitizing bandpass sigma-delta modulator chip's production-time testing and in-the-field diagnostics. The technique can also be extended to mixed-signal communication SoC built-in-self-test.     

Sigma-delta调制器的设计和降采样原理分析

根据实际的研发过程,详细讨论了音频ADC中Sigma-delta调制器的设计过程,即调制器系数的生成方法,并且深入的研究了降采样的作用和工作原理,并在此基础上给出了降采样滤波器的具体实现方法.     

Opamp gain insensitive MASH sigma delta modulator for wide bandwidth applications

This work presents a means to enhance the immunity of non-ideal opamp gain effect of the fourth order multi-stage noise shaped (MASH) sigma-delta modulator (SDM) for wide bandwidth applications. The first stage of the SDM is a low-distortion single-loop second order SDM, while the second stage is a low-distortion interpolative second order SDM with Chebyshev type II filter technique. Theoretically, the conventional MASH SDM is impacted by the nonlinear finite gain of the operational amplifier. This impact may have two main phenomena. First, it leaks the incompletely corrected quantization error to the output. Secondly, the nonlinearity causes the harmonic distortion of the input signal. The proposed architecture can reduce the distortion and the sensitivity of the nonlinear finite opamp gain to improve the performance by using low-distortion technique in the MASH SDM. Furthermore, the lower power budget and simplified digital cancellation logic can be achieved. The experimental results indicate that the dynamic range (DR) can reach 87dB with power dissipation of 65 mW. A test SDM chip for Asymmetric Digital Subscriber Line (ADSL) application is designed and implemented by TSMC 0.25 um 1P5M process. Jen-Shiun Chiang was born in Taichung Taiwan, ROC in 1960. He received the B.S. degree in electronics engineering from Tamkang University, Taipei, Taiwan in 1983. In 1988, he received the M.S. degree in electrical engineering from University of Idaho, Moscow Idaho, USA. In 1992, he received the Ph.D. degree in the electrical engineering from Texas A & M University, College Station Texas, USA. He joined the faculty member of the Department of Electrical Engineering at Tamkang University in 1992. Currently, he is a Professor and Department Chair of the Department of Electrical Engineering at Tamkang University. Dr. Chaings research interest includes computer arithmetic, computer architecture, digital signal processing for VLSI architecture, architecture for image data compressing, analog to digital data conversion, and low power circuit design. Hsin-Liang Chen was born in Taipei, Taiwan, in 1974. He received the B.S. degree and M.S. degree in the electrical engineering from Tamkang University, Taipei, Taiwan, in 1997 and 2003, respectively. He is currently working toward the Ph.D. degree at Tamkang University. His research interest focuses on mixed-signal CMOS circuit, sigma delta ADC, and low power circuit.     

Σ-Δ模拟/数字转换器综述

Σ-ΔA/D转换器是利用速度换取精度的高精度模拟/数字转换器。文章分析了Σ-ΔA/D转换器的产生、组成和优势,重点介绍了Σ-Δ调制器结构及其性能指标,简要介绍了数字抽取滤波器。对Σ-ΔA/D转换器国内外发展状况进行了全面的分析。在此基础上,论述了Σ-ΔA/D转换器未来的发展趋势。     

Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST

In order to perform an on-chip test for characterizing both static and transmission parameters of embedded analog-to-digital converters (ADCs), this paper presents an oscillator-based reconfigurable sinusoidal signal generator which can produce both high and low frequency sinusoidal signals by switching the oscillator into different modes. Analog and digital signals can additionally be produced concurrently in both modes to provide not only test stimuli, but also reference responses for the ADC built-in self-test. The generated oscillation signal amplitude and frequency can be easily and precisely controlled by simply setting the oscillator clock frequency and initial condition coefficients. Except for a 1-bit digital-to-analog converter and smoothing filter, this proposed generator is constructed entirely by digital circuits, and hence easily integrates this silicon function and verifies itself before testing the ADCs.

An analytical phase noise model of charge pump mismatch in sigma-delta frequency synthesizer

Although some papers have qualitatively analyzed the effect of charge pump mismatch on phase noise and spurs in sigma-delta fractional-N frequency synthesizer, few of them have addressed this topic quantitatively. An analytical model is proposed in this paper to describe the behavior of charge pump mismatch and the corresponding phase noise. Numerical simulation shows that this model is of high accuracy and can be applied to the analysis of in-band phase induced by the charge pump mismatch in sigma-delta fractional-N PLL frequency synthesizer. Most importantly, this model discloses that 6 dB reduction of in-band phase noise due to charge pump mismatch can be achieved by halving the charge pump mismatch ratio. After studying the typical topologies of sigma-delta modulators (SDM), we proposed some strategies on the selection of SDM in frequency synthesizer design. Our analytical model also indicates that eliminating the charge pump mismatch is one major path towards the in-band phase noise reduction of the sigma-delta frequency synthesizer. Xiaojian Mao was born in Jiangsu Province, China, in 1978. He received the B.S. degree in electronic engineering from Jilin University, Changchun, China, in 2000. He is currently pursuing the Ph.D. degree in circuits and systems at Department of Electronic Engineering of Tsinghua University, Beijing, China. His current research includes frequency synthesizers and phase-locking and clock recovery for high-speed data communications. And His PhD thesis title is “Design and Analysis of Sigma-Delta Fractional-N PLL Frequency Synthesizer.” Huazhong Yang received BS, MS, and PhD Degrees in electronics engineering from Tsinghua University, Beijing, in 1989, 1993, and 1998, respectively. He is a Professor and Head of the Circuits and Systems Division in the Department of Electronic Engineering at Tsinghua University, Beijing. His research interests include CMOS radio-frequency integrated circuits, VLSI system structure for digital communications and media processing, low-voltage and low-power circuits, and computer-aided design methodologies for system integration. He has authored and co-authored 6 books and more than 100 journals and conference papers. He was the winner of Chinas National Palmary Young Researcher Award in 2000. Hui Wang received the B.S. degree from Department of Radio Electronics, from Tsinghua University, Beijing, China. She was a visiting scholar at Stanford University, CA, USA from February 1991 to September 1992. Currently she is a Professor of the Circuits and Systems Division in the Department of Electronic Engineering and the deputy dean of academic affairs office at Tsinghua University, Beijing, China. Her research interests include modeling and simulation of radio-frequency CMOS integrated circuits, automatic design methodology for low voltage and low-power integrated circuits, and interconnect modeling and synthesis for deep submicron system-on-a-chip. She has authored and co-authored 4 books and over 70 papers. She was a primary research of TADS-C4 which gained a third-grade prize for the national progress in science and technology in China in 1993.     

Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist

A synthesis tool consisting of coefficient synthesis of architecture, circuit specifications synthesis, and CMOS operational-amplifier (op-amp) synthesis for discrete-time sigma-delta modulators (SDMs) is presented. In circuit specifications synthesis, several major circuit non-idealities are discussed and modeled. A precise performance prediction with a new design flow of specification synthesis is proposed. A hybrid design methodology composed of equation-based and simulation-based approaches for synthesizing fully differential two-stage and folded-cascode op-amps in technology is also presented. Experimental results show that the peak signal-to-noise and distortion ratio (PSNDR) of the fourth-order feed-forward (FF) SDM with an oversampling ratio (OSR) of 64 and a bandwidth of 20 KHz estimated by the proposed synthesis tool is 94.19 dB, and the result of the circuit simulation with folded-cascode op-amp is 93.03 dB. The estimated PSNDR of the third-order multiple-feedback (MF) SDM with an OSR of 32 and a bandwidth of 256 KHz is 59.52 dB, and the HSPICE simulation result is 55.39 dB.     

应用于脑电监控的低功耗开关电容Delta-Sigma调制器

本文介绍了一个应用于便携式脑电监控生物医学系统的三阶单环Delta-Sigma调制器。为了降低功耗,调制器中的环路滤波器采用开关电容电路实现。调制器在0.35-μm 2P4M标准CMOS工艺下流片。核心面积为365×290μm2。实验结果显示,输入100Hz的正弦波,在64倍过采样率下,调制器能达到68dB的动态范围。供电电压为2.5V,整个芯片消耗515μW的功耗。适用于便携脑电监控系统。