整数5/3小波变换的VLSI结构设计

在JPEG 2000中,无损图像压缩是采用整数5/3小波变换实现的.JPEG 2000也给出了5/3小波基于提升方法的算法.对提升方法的整数5/3小波变换算法进行了研究,针对二维的变换提出一种VLSI结构.该结构由4个模块构成,模块之间并行运行,模块内部采用流水线技术.对多级变换,级间的运算还可交叉,体现了提升方法的优势,较大地提高了硬件效率.其主要优点是消耗资源少且运算速度高,同时也适用于其他整数小波变换.     

二维离散5/3小波变换并行VLSI结构设计

提出了一种基于提升算法的二维离散5/3小波变换(DWT)高效并行VLSI结构设计方法。该方法使得行和列滤波器同时进行滤波,采用流水线设计方法处理,在保证同样的精度下,大大减少了运算量,提高了变换速度,节约了硬件资源。该方法已通过了VerilogHDL行为级仿真验证,可作为单独的IP核应用在JPEG2000图像编、解码芯片中。该结构可推广到9/7小波提升结构。     

JPEG2000并行阵列式小波滤波器的VLSI结构设计

提出一种基于提升算法实现JPEG2000编码系统中的二维离散小波变换(Discrete Wavelet Transform)的并行阵列式的VLSI结构设计方法.利用该方法所得结构由两个行处理器,一个列处理器以及少量行缓存组成;行列处理器内部是由并行阵列式的处理单元组成;能使行和列滤波器同时进行滤波,用优化的移位加操作替代乘法操作.整个结构采用流水线的设计方法处理,在保证同样的精度下,大大减少了运算量和提高了硬件资源利用率,几乎达到100％,加快了变换速度,也减少了电路的规模.该结构对于N×N大小的图像,处理速度达到O(N²/2)个时钟周期.二维离散小波滤波器结构已经过FPGA验证,并可作为单独的IP核应用于正在开发的JPEG2000图像编解码芯片中.     

一种适合JPEG2000的离散小波变换VLSI统一结构

提出了一种基于提升算法(1ifting)的离散小波变换(DWT)统一结构。它无需额外的边界延拓过程，经配置后可适用于JPEG2000中的无损或有损小波变换。通过将边界延拓过程内嵌于离散小波变换中，可以降低功耗，减少所需内存。为了达到更高的处理速度和硬件利用率，采用了流水线和折叠结构。这种高效紧凑的离散小波变换结构适用于JPEG2000编码器和各种实时图像／视频应用系统．     

JPEG2000小波变换器的VLSI结构设计

新一代静止图像压缩标准JPEG2000将离散小波变换(DWT)作为其核心变换技术,并推荐采用推举体制(lifting)快速算法来实现.空间组合推举体制算法(SCLA)大大降低了lifting的运算量.当选用9/7小波滤波器时,SCLA的乘法运算量只有lifting的7/12.本文提出了一种实现SCLA算法的VLSI结构,降低了基于lifting实现的运算量, 加快了变换的速度,减小了电路的规模.本文的二维正反小波变换器已经作为单独的IP核应用于我们目前正在开发的JPEG2000图像编解码芯片中.     

JPEG2000中的小波算法

本文介绍最新图像压缩标准JPEG2000中的小波算法,简要讨论与该算法相关的JPEG2000的重要特性(如感兴趣区域、渐进传输等)及其他一些问题。展望小波算法用于视频压缩中的前景。分析存在的困难并给出一个切实可行的解决办法。     

二维9/7小波变换VLSI设计

为了提高JPEG2000图像压缩速度,提出一种基于提升算法的二维离散9/7小波变换(DWT)Mesh结构的VLSI设计方案,利用这种Mesh结构的VLSI能够实现并行处理一个图像的所有像素点.这种并行处理的Mesh结构可提高小波变换电路速度,以及图像压缩的速度.     

JPEG2000及其编码系统的实现

随着多媒体技术应用领域的扩大，小波图像压缩研究日趋成熟。因此，国际标准化组织(ISO)指定了新一代的图像压缩标准：JPEG2000。首先介绍了JPEG2000的特点，然后介绍了JPEG2000的编码系统的实现过程，重点讨论了JPEG2000的技术核心：离散小波变换和EBCOT技术。最后，通过使用VC^ 6．0实现JPEG2000的编码算法，并对两种图像压缩格式进行了比较，给出了一个详细的实验结果。     

JPEG2000中5/3离散小波多层变换FPGA实现研究

基于新一代图像压缩国际标准JPEG 2000,介绍一种快速、有效的多层5/3小波变换的VLSI设计结构,该方法使用两组一维变换实现,用移位-相加代替乘法操作,整体设计采用了流水线设计。利用双端口RAM和地址生成模块的调度完成小波变换的分裂、边界延拓工作,不需另外增加模块。二维离散小波变换滤波器结构的设计采用Verilog HDL进行RTL级描述,已经通过了FPGA验证,并可作为单独的IP核应用于图像编解码芯片中。     

一种基于JPEG2000标准的高性能FIR滤波器组设计

文章提出了一种基于JPEG2000标准中无损压缩滤波器组的VLSI实现方法，在文章中我们充分利用了小波系数是2的幂的和的形式的性质，FIR滤波器的线性性质以及流水线的设计技术，不需要乘法器就完成了小波变换，本文所提出的设计方法的特征：没有为小波变换专门设计下采样模块，而是通过一个时钟分频方案来完成；通过移位加来代替乘法运算；无“等待时间”的开销；吞吐量高，芯片面积小，实验结果表明本文提出的方法是一种适合于VLSI实现的设计方案。     

JPEG2000标准中MQ编码器的VLSI结构设计

MQ编码器是JPEG 2000标准中重要的无损压缩算法,可获得很高的压缩效率.但因其算法复杂度高,执行速度慢,使其应用受到很大限制.为了获得高速处理能力,设计一种高速MQ编码器的VLSI结构,采用三级流水线结构,对算法进行优化,并改进概率估计表内容.设计使用Verilog进行编程,最后通过Modelsim 6.1进行仿真.实验结果表明,该设计极大地提高了编码速度.这里的研究对于JPEG 2000在实际中的应用有着重要的意义.     

一种基于提升的二维离散小波变换VLSI架构

离散小波变换(Discrete Wavelet Transform,DWT)需要较多的运算量以及较大的存储器空间,为了使之适用于实时的图像处理应用,就需要开发特殊的架构和芯片来提高离散小波变换的运算性能。基于提升的二维DWT提出了一种新型的VLSI结构——LLSP架构,其结合逐级和基于行的架构这两者特点,带来了硬件开销和存储器空间的降低,并可以用于多提升步骤的扩展以及多级二维离散小波变换。     

JPEG2000中位平面编码的VLSI结构设计

位平面编码用于对量化的离散小波变换的码块数据进行编码.通过对位平面编码算法的分析和C语言验证,给出了位平面编码的四种基本编码操作和三个编码通道具体的VLSI结构实现.对位平面编码器的VLSI结构进行了仿真和综合,在图像验证系统上用逻辑分析仪实际测量的结果与仿真结果一致.该位平面编码器可在50 MHz的主频下,完成32×32码块数据的编码.所设计的位平面编码器已经作为单独的IP核应用于目前正在开发的JPEG2000图像编码芯片中.     

Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations

This paper proposes two JPEG 2000 compliant architectures: one for DWT (Discrete Wavelet Transform) and one for IWT (Integer Wavelet Transform) implementation. First of all some theoretical issues about DWT and IWT are discussed, then, starting from transforms characteristics, the architectures are presented showing both performance and cost. In the literature many DWT architectures have been proposed; our implementation is a new architecture that computes the DWT using filters of interest for the forthcoming JPEG 2000 standard. Moreover, we propose a Lifting Scheme based architecture for IWT, JPEG 2000 compliant too. The proposed architectures are able to support real-time streams: the DWT one, which is made of 20,000 cells, with an input throughput of 160 Msamples per second and a clock frequency of 160 MHz, the IWT one, consisting of 50,000 cells, with an input throughput of 4.5 Msamples per second and an internal clock frequency of 108 MHz.     

JPEG2000中小波滤波器的定点分析及其VLSI实现

对JPEG2 0 0 0中推荐的 5 /3整数滤波器和 9/7实数滤波器进行了硬件实现时所需要的有限精度分析 ;确定了小波变换过程中各个参数的最佳数据宽度 ,还确定了整个变换系统的数据通路的数据宽度。基于lifting的小波变换的特点结合嵌入式延拓算法提出了两种小波变换———折叠结构和长流水线结构 ;对两种结构进行了分析比较。最后 ,对折叠结构和相关的其它结构在所需存储单元的数量、存储单元的访问次数、处理能力以及功耗等方面进行了分析比较 ,可以看出文中提出的结构在性能上有明显优点。     

JPEG2000中DWT-EBCOT联合的高效低存储VLSI结构

针对JPEG2000硬件实现中小波变换与编码之间占用大量存储的问题,该文提出一种基于码块的存储方案。通过对码块大小片内存储最大程度的复用以及对其高效简单的调度控制,从面积和功耗两方面减小了硬件实现的开销。在实现中,采用基于行的提升变换结构和比特平面并行的编码方式,提高了效率,确保整个过程的实时处理。实验结果表明：在实时编码要求下,对分辨率为512512的图像分片进行四级9/7或者5/3小波分解,码块大小为3232,采用本文结构所用的存储量与直接使用外部存储器的方法相比可减少80%以上。整个结构已通过FPGA验证,且系统时钟可以工作在100MHz。     

VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters

In this paper, a VLSI architecture for lifting-based shape-adaptive discrete wavelet transform (SA-DWT) with odd-symmetric filters is proposed. The proposed architecture is comprised of a stage-based boundary extension strategy and the shape-adaptive boundary handling units. The former could reduce the complexity of multiplexers that are introduced to solve the shape-adaptive boundary extension. The latter consists of two multiplexers and can solve the shape-adaptive boundary extension locally without any additional register. Two case studies are presented, including the JPEG 2000 default (9, 7) filter and MPEG-4 default (9, 3) filter. According to comparison results with previous architectures, the efficiency of the proposed architectures is proven.Chao-Tsung Huang was born in Kaohsiung, Taiwan in 1979. He received the B.S. degree from the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan in 2001. He is currently working toward the Ph.D. degree at the Graduate Institute of Electronics Engineering, National Taiwan University. His major research interests include VLSI design and implementation for 1-D, 2-D, and 3-D Discrete Wavelet Transform. cthuang@video.ee.ntu.edu.twPo-Chih Tseng was born in Tao-Yuan, Taiwan in 1977. He received the B.S. degree in Electrical and Control Engineering from National Chiao Tung University in 1999 and the M.S. degree in Electrical Engineering from National Taiwan University in 2001. He currently is pursuing the Ph.D. degree at the Graduate Institute of Electronics Engineering, Department of Electrical Engineering, National Taiwan University. His research interests include VLSI design and implementation for signal processing systems, energy-efficient reconfigurable computing for multimedia systems, and power-aware image and video coding systems. pctseng@video.ee.ntu.edu.twLiang-Gee Chen (S84–M86–SM94–F01) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1979, 1981, and 1986, respectively.In 1988, he joined the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R.O.C. During 1993–1994, he was a Visiting Consultant in the DSP Research Department, AT&T Bell Labs, Murray Hill, NJ. In 1997, he was a Visiting Scholar of the Department of Electrical Engineering, University of Washington, Seattle. Currently, he is Professor at National Taiwan University, Taipei, Taiwan, R.O.C. His current research interests are DSP architecture design, video processor design, and video coding systems.Dr. Chen has served as an Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY since 1996, as Associate Editor of the IEEE TRANSACTIONS ON VLSI SYSTEMS since 1999, and as Associate Editor of IEEE TRANSACTIONS CIRCUITS AND SYSTEMS II since 2000. He has been the Associate Editor of the Journal of Circuits, Systems, and Signal Processing since 1999, and a Guest Editor for the Journal of Video Signal Processing Systems. He is also the Associate Editor of the PROCEEDINGS OF THE IEEE. He was the General Chairman of the 7th VLSI Design/CAD Symposium in 1995 and of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He is the Past-Chair of Taipei Chapter of IEEE Circuits and Systems (CAS) Society, and is a member of the IEEE CAS Technical Committee of VLSI Systems and Applications, the Technical Committee of Visual Signal Processing and Communications, and the IEEE Signal Processing Technical Committee of Design and Implementation of SP Systems. He is the Chair-Elect of the IEEE CAS Technical Committee on Multimedia Systems and Applications. During 2001–2002, he served as a Distinguished Lecturer of the IEEE CAS Society. He received the Best Paper Award from the R.O.C. Computer Society in 1990 and 1994. Annually from 1991 to 1999, he received Long-Term (Acer) Paper Awards. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on circuits and systems in the VLSI design track. In 1993, he received the Annual Paper Award of the Chinese Engineer Society. In 1996 and 2000, he received the Outstanding Research Award from the National Science Council, and in 2000, the Dragon Excellence Award from Acer. He is a member of Phi Tan Phi. lgchen@video.ee.ntu.edu.tw