Analog VLSI Circuits for Competitive Learning Networks

An investigation is made concerning implementations of competitive learning algorithms in analog VLSI circuits and systems. Analog and low power digital circuits for competitive learning are currently important for their applications in computationally-efficient speech and image compression by vector quantization, as required for example in portable multi-media terminals. A summary of competitive learning models is presented to indicate the type of VLSI computations required, and the effects of weight quantization are discussed. Analog circuit representations of computational primitives for learning and evaluation of distortion metrics are discussed. The present state of VLSI implementations of hard and soft competitive learning algorithms are described, as well as those for topological feature maps. Tolerance of learning algorithms to observed analog circuit properties is reported. New results are also presented from simulations of frequency-sensitive and soft competitive learning concerning sensitivity of these algorithms to precision in VLSI learning computations. Applications of these learning algorithms to unsupervised feature extraction and to vector quantization of speech and images are also described.     

A Robust Analog VLSI Reichardt Motion Sensor

Silicon imagers with integrated motion-detection circuitry have been developed and tested for the past 15 years. Many previous circuits estimate motion by identifying and tracking spatial or temporal features. These approaches are prone to failure at low SNR conditions, where feature detection becomes unreliable. An alternate approach to motion detection is an intensity-based spatiotemporal correlation algorithm, such as the one proposed by Hassenstein and Reichardt in 1956 to explain aspects of insect vision. We implemented a Reichardt motion sensor with integrated photodetectors in a standard CMOS process. Our circuit operates at sub-microwatt power levels, the lowest reported for any motion sensor. We measure the effects of device mismatch on these parallel, analog circuits to show they are suitable for constructing 2-D VLSI arrays. Traditional correlation-based sensors suffer from strong contrast dependence. We introduce a circuit architecture that lessens this dependence. We also demonstrate robust performance of our sensor to complex stimuli in the presence of spatial and temporal noise.     

一种多级运动估值VLSI结构的设计

提出了一种新的多级运动估值器的结构 ,它支持低比特视频编码器的高级预测模式 ,如H.2 63和 MPEG- 4。该 VLSI结构的所有级别中共用一个基本的搜索单元 ( BSU) ,减小了芯片尺寸。另外 ,由于它为计算 8× 8块的绝对误差和 SAD提供了一种对存储器数据流的控制电路 ,因此 ,对于高级预测模式 ,可同时获得 1个宏块运动矢量和每个宏块中的 4个子块运动矢量。这种尺寸较小的运动估值电路可以获得与全搜索块匹配算法 ( FSBMA)相似的编码效果     

形状编码的二值运动估值及其VLSI结构优化设计

文章提出一种高效的VLSI结构，实现MPEG－4视频编码标准中二值形状的运动估值算法。我们称这种结构为DDBME。其主要由一个基于一维脉动阵列的数据分配器和16＊32bit的搜索区域缓冲器组成。在DDBME中，采用数据位并行处理技术进行块匹配算法中绝对误差和（SAD）的计算。     

一种H.264运动估计器的VLSI设计

MPEG4AVC／ITU—T H．264视频编码标准中所采用的多模式运动估计算法与传统的MPEG4、H．263 高级预测模式相比较而言，编码效率和性能都大大提高。但其诸如模式决策等问题却给运动估计器，特别是硬件运动估计器带来非常大的运算复杂度。本文提出一种H．264运动估计器硬件结构，它采用了新的模式决策算法和快速运动估计算法。仿真结果证明，这两种算法不但能使运动估计器降低其硬件实现成本，而且能减少模式决策和运动估计的时间。     

一种适合于低代价、低功耗VLSI实现的块匹配运动估值算法

本文给出了一种用于块匹配运动估值的改进的多分辨率望远镜搜索(MRTlcS)算法.它以望远镜的逆向搜索取代了传统的望远镜搜索,这一改进有效地降低了VLSI实现时对片上存储器容量和带宽的要求.此外本文还采用运动跟踪和自适应搜索窗技术来减小运动估值的计算复杂性.适合于低代价、低功耗VLSI实现是新算法的显著特点.模拟结果表明新算法要求的平均运算量仅为MRTlcS算法的30%左右,而仍然可以得到相似的视频解码图质量.本文也给出了新算法和MRTlcS算法用于VLSI实现时的硬件代价和功耗比较.     

A Smart-Scanning Analog VLSI Visual-Attention System

We have implemented a hardware model of selective visual attention within the neuromorphic, analog VLSI paradigm. The system includes a highly-parallel winner-take-all selection with excitatory and inhibitory influences. The selection specifies positions of attention based on an array of intensity levels, which comprise a primitive saliency map. The excitation and inhibition control the strategy for shifts of attention from one position to the next. The combination of these fundamental building blocks demonstrates emergent properties that can be observed in real time due to the parallel hardware implementation. The system behaves as a smart-scanning sensor array. The basic characteristics of the scanning pattern are controlled by setting a number of analog parameters. In this paper we describe the system, focusing on the role that inhibition plays in the redirection of attention. We show experimental results from one-dimensional implementations of the hardware model. Analysis that explains the expected behavior for the two-element mode of operation is presented. The theoretical predictions are compared to experimental results.     

VLSI Architecture Design of Fractional Motion Estimation for H.264/AVC

The H.264/AVC Fractional Motion Estimation (FME) with rate-distortion constrained mode decision can improve the rate-distortion efficiency by 2–6 dB in peak signal-to-noise ratio. However, it comes with considerable computation complexity. Acceleration by dedicated hardware is a must for real-time applications. The main difficulty for FME hardware implementation is parallel processing under the constraint of the sequential flow and data dependency. We analyze seven inter-correlative loops extracted from FME procedure and provide decomposing methodologies to obtain efficient projection in hardware implementation. Two techniques, 4×4 block decomposition and efficiently vertical scheduling, are proposed to reuse data among the variable block size and to improve the hardware utilization. Besides, advanced architectures are designed to efficiently integrate the 6-taps 2D finite impulse response, residue generation, and 4×4 Hadamard transform into a fully pipelined architecture. This design is finally implemented and integrated into an H.264/AVC single chip encoder that supports realtime encoding of 720×480 30fps video with four reference frames at 81 MHz operation frequency with 405 K logic gates (41.9% area of the encoder).

Low-power Analog VLSI Implementation of Wavelet Transform

For applications requiring low-power, low-voltage and real-time, a novel analog VLSI implementation of continuous Marr wavelet transform based on CMOS log-domain integrator is proposed.Mart wavelet is approximated by a parameterized class of function and with Levenbery-Marquardt nonlinear least square method,the optimum parameters of this function are obtained.The circuits of implementating Mart wavelet transform are composed of analog filter whose impulse response is the required wavelet.The filter design is based on IFLF structure with CMOS log-domain integrators as the main building blocks.SPICE simulations indicate an excellent approximations of ideal wavelet.     

An Analog VLSI, Scale Invariant Method for Edge Detection

A simple technique for detecting adjustable contrast in a visual scene is presented. The circuit elements can be used to detect contrast in any array of sensors or processing elements where spatial relationships among neighboring elements define contrast or the presence of an edge. This technique eliminates the need for a differential pair, thereby allowing more than two inputs to be compared for contrast in a single processing step. The circuit elements first smooth erroneous edges in the array through the use of a resistive network, then, the mean (scaled by an adjustable amount) of a pixel and its neighbors is compared to the harmonic mean of the same pixels to detect the presence of contrast within the pixel neighborhood. Comparison between the mean and harmonic mean allows the detection of contrast to be scale-invariant as long as the transistors remain in subthreshold operation. This circuit offers the massively parallel processing inherent to focal plane processing within an 18% fill factor in a 2 m process, 6.8 W typical power dissipation per element, and 0.67 ms response time at low power subthreshold operation. Results for a proof of concept, 8×8 array of pixels with light inputs, as well as a purely electronic input, 4×4 array are presented.     

VLSI Design for High-Precision Three-Dimensional Depth Perception Chip

This paper presents a Very large scale integration (VLSI) design method for Three-dimensional (3D) depth perception chip based on infrared coding structure light. The primary sub-modules on the chip contain the speckle pattern preprocessing module, block-matching disparity estimation, depth mapping and post-processing. The chip employs pipelining technology, and after Application specific integrated circuit (ASIC) verification, it proves that our chip has more advantages in performance of depth precision (12bits, 1mm @ 1m), image resolution (1280×960), time delay (less than 17ms), range limit (0.4～6m). It also can generate more stable and smooth depth map in real-time, which can be used in 3D recognition, motion capture or scene perception.     

一种快速高效MPEG-4运动估计硬件结构的研究和实现

提出一种高度并行和多流水线处理的硬件结构,实现MPEG-4视频部分的全搜索块匹配运动估计算法.该硬件结构能实时地通过全搜索块匹配运动估计算法来搜索每个像素块最佳匹配运动向量,具有计算速度高、运动向量准确、较少的内置存储器要求、低运行时钟和低功耗等诸多优点,从而可满足移动视频业务和高清晰视频业务的需求.该硬件结构基于富士通的CE66库实现.     

一种新的使用两种比特分辨率图象的块匹配运动估计算法及其低功耗VLSI结构

本文给出了一种新的块匹配运动估计算法,它根据视频图像内容的复杂程度自适应地选择常规的或者低比特分辨率的图像来进行块匹配,并且采用了一种混合使用两种比特分辨率图像的新望远镜搜索算法.模拟结果表明,新算法具有较低的计算复杂性,并且能够保证较好的视频质量.基于该算法,我们设计了一种新的脉动阵列结构的搜索引擎.该引擎具有可分割的数据通道,从而在使用低比特分辨率图像进行块匹配时能够通过加强处理的并行性来提高吞吐率.新的运动估计器可工作在较低的时钟频率和电源电压之下,具有低的功耗消耗.     

A Pulsed Communication/Computation Framework for Analog VLSI Perceptive Systems

This paper presents the principles, the main propertiesand some applications of a pulsed communication system adaptedto the needs of the analog VLSI implementation of perceptivesystems. The system takes advantage of the fact that activitiesin perception tasks are often sparsely distributed over a largenumber of elementary processing units (cells) and facilitatesaccess to the communication channel for the more active cells.The resulting architecture can be advantageously used to setup connections between distant cells on the same chip or point-to-pointconnections between cells on different chips when direct wiringis prohibitive. Cells communicate in an asynchronous fashionwhich conserves the fine time relationships of events. The systemalso lends itself to the simple circuit implementation of typicalbiologically inspired connectivity patterns such as projectionof the activity of one cell on a region (its projective field)of the next neural processing layer, which can be on a differentchip in an actual implementation, as is the case for one of theapplications presented: an oriented-edges enhancement system.     

一种运动自适应去隔行技术及其VLSI结构

提出一种有效的运动自适应去隔行算法.该算法通过对同极性的相邻场进行运动检测,把插值点所处的区域分为快速运动区域、慢速运动区域和静止区域,对不同的区域采用不同的插值算法.在边缘检测方面,采用改进型ELA算法克服了传统的ELA算法处理水平边缘方面的不足,使边缘得到有效保护.与运动补偿算法相比,该算法计算复杂度较低,易于VL...     

Analog VLSI Implementation of Artificial Neural Networks with Supervised On-Chip Learning

Analog VLSI on-chip learning Neural Networks represent a mature technology for a large number of applications involving industrial as well as consumer appliances. This is particularly the case when low power consumption, small size and/or very high speed are required. This approach exploits the computational features of Neural Networks, the implementation efficiency of analog VLSI circuits and the adaptation capabilities of the on-chip learning feedback schema.Many experimental chips and microelectronic implementations have been reported in the literature based on the research carried out over the last few years by several research groups. The author presents and discusses the motivations, the system and circuit issues, the design methodology as well as the limitations of this kind of approach. Attention is focused on supervised learning algorithms because of their reliability and popularity within the neural network research community. In particular, the Back Propagation and Weight Perturbation learning algorithms are introduced and reviewed with respect to their analog VLSI implementation.Finally, the author also reviews and compares the main results reported in the literature, highlighting the efficiency and the reliability of the on-chip implementation of these algorithms.     

Analog VLSI Excitatory Feedback Circuits for Attentional Shifts and Tracking

In this paper we present analog very large-scale integrated(VLSI) circuits that perform the selection process for attentivevisual processing. These circuits use excitatory feedback ina winner-take-all computation to produce a hysteresis in theselection from one location to the next. We present several alternativeforms of excitation that can be used to enhance surrounding regionsof the presently attended location. Each form of excitation isdiscussed and experimental results from a one-dimensional arrayare presented. We also demonstrate the performance of these circuitswithin a system that receives optical inputs and outputs a singlevoltage that encodes the position of attention. The system demonstratesthe potential use of these excitatory feedback circuits for electronictracking of a stimulus within a noisy environment.     

一种高效地实现运动估计算法的VLSI结构

本文提出了一种全新的低延滞、高吞吐率、可编程的ＶＬＳＩ树型结构，它能十分有效地实现ＦＳＡ和ＴＳＳＡ运动估计算法。该结构比其它树型结构少１／３的处理单元（ＰＥ），而且ＰＥ单元的延时减少一半。独特的ＭＥ窗缓冲结构使Ｉ／Ｏ带宽和Ｉ／Ｏ管脚大大减小，交叉流水线技术使硬件利用率可达到１００％。这些特点使得该结构适合ＶＬＳＩ实现。     

VLSI使用寿命的一种估计方法

文章提出了一种ＶＬＳＩ使用的实用估计方法，该方法充分考虑了工作条件对集成电路寿命的影响，使估计结果更切合实际。     

Motion detection and stochastic resonance in noisy environments

Several motion detection schemes are considered and their responses to noisy signals investigated. The schemes include the Reichardt correlation detector, shunting inhibition and the Horridge template model. These schemes are directionally selective and independent of the direction of change in contrast. They function by using spatial information and comparing it at successive time intervals. A rudimentary noise analysis is performed on the Reichardt and inhibition detectors to compare their natural robustness against noise. Using these detectors, stochastic resonance (SR) is applied, which is characterised by an improvement in response when noise is added to the input signal. It is found that the performance of the detectors degrades with the addition of noise. Employing Stocks' suprathreshold SR, an improvement can be gained when considering a network of detectors. Furthermore, when using an incorrect threshold setting for the template model, SR can be displayed.