基于HLA的三维虚拟环境

在分析了HLA体系结构及运行支撑框架(RTI)的基础上,提出了一个基于HLA的三维虚拟环境的设计和实现方案。阐明了此类系统的设计方法,着重分析了系统实现中涉及的仿真对象模型、信息交互机制、程序控制逻辑、坐标转换、实时性等关键技术问题和解决方案。最后在使用WindowsNT4.0的PIII高档微机平台上实现了该系统。实验表明,在综合分布交互系统SSS中,该分系统可实现与其它分系统的正确交互,场景刷新速率最高可达20帧/秒,基本满足实时性要求。     

HAL: A High-Speed Logic Simulation Machine

The architecture of a very-high-speed logic simulation machine (HAL), which can simulate up to one-half million gates and 2M-byte memory chips at a 5 ms clock speed, is described. This machine makes it possible to debug the total system?CPU, main memory, cache memory and control storage?before the actual machine is fabricated. HAL employs parallel and pipeline processing, and event-driven, block-level logic simulation. The prototype system for a 32-processor system has been constructed and is now in use as a tool for large mainframe computer development. HAL is more than a thousand times faster than existing software logic simulators.     

The Effects of Modeling on Simulator Performance

Gate-level simulators are usually thought of in terms of their benefits to logic designers, while behavioral simulators are considered to be the province of system architects. However, the behavioral modeling capabilities of a multilevel gate/behavioral simulator significantly enhanced the performance and accuracy of what are essentially gate-level simulations. The Behave simulator is a multilevel simulator that can simulate circuits at several levels of abstraction?behavioral level, gate level, or a mixture. Zero delay and rank order capability are also available in Behave and can be used to advantage. For example, in a simulation of an array multiplier involving 10,000 vectors, the time decreased from 16 hours to 38 minutes, simply because the elements were rank ordered. This range of processing is possible because of the flexibility in software for general-purpose CPUs.     

Speeding Up Cycle Based Logic Simulation Using Graphics Processing Units

Verification has grown to dominate the cost of electronic system design, consuming about 60% of design effort. Among several verification techniques, logic simulation remains the major verification technique. Speeding up logic simulation results in great savings and shorter time-to-market. We parallelize logic simulation using Graphics Processing Units (GPUs). In the past, GPUs were special-purpose application accelerators, suitable only for conventional graphics applications. The new generations of GPU architecture provide easier programmability and increased generality while maintaining the tremendous memory bandwidth and computational power of traditional GPUs. We develop a parallel cycle-based logic simulation algorithm that uses And Inverter Graphs (AIGs) as design representations. AIGs have proven to be an effective representation for various design automation applications, and we obtain similar benefits for speeding up logic simulation. We develop two clustering algorithms that partition the gates in the designs into independent blocks. Our algorithms exploit the massively parallel GPU architecture featuring thousands of concurrent threads, fast memory, and memory coalescing for optimizations. We demonstrate up-to 5x and 21x speedups on several benchmarks using our simulation system with the first and second clustering algorithms, respectively. Our work ultimately results in significant reduction in the overall design cycle.     

An FPGA stereo matching unit based on fuzzy logic

Stereo matching is one of the most used algorithms in real-time image processing applications such as positioning systems for mobile robots, three-dimensional building mapping and recognition, detection and three-dimensional reconstruction of objects. In order to improve the performance, stereo matching algorithms often have been implemented in dedicated hardware such as FPGA or GPU devices. In this paper an FPGA stereo matching unit based on fuzzy logic is described. The proposed algorithm consists of three stages. First, three similarity parameters inherent to each pixel contained in the input stereo pair are computed. Then, the similarity parameters are sent to a fuzzy inference system which determines a fuzzy-similarity value. Finally, the disparity value is defined as the index which maximizes the fuzzy-similarity values (zero up to d_max). Dense disparity maps are computed at a rate of 76 frames per second for input stereo pairs of 1280 × 1024 pixel resolution and a maximum expected disparity equal to 15. The developed FPGA architecture provides reduction of the hardware resource demand compared to other FPGA-based stereo matching algorithms: near to 72.35% for logic units and near to 32.24% for bits of memory. In addition, the developed FPGA architecture increases the processing speed: near to 34.90% pixels per second and outperforms the accuracy of most of real-time stereo matching algorithms in the state of the art.     

Interactive Geometric Simulation of 4D Cities

We present a simulation system that can simulate a three-dimensional urban model over time. The main novelty of our approach is that we do not rely on land-use simulation on a regular grid, but instead build a complete and inherently geometric simulation that includes exact parcel boundaries, streets of arbitrary orientation, street widths, 3D street geometry, building footprints, and 3D building envelopes. The second novelty is the fast simulation time and user interaction at interactive speed of about 1 second per time step.     

Performance evaluation of the IMPS multiprocessor system

The performance of the IMPS multiprocessor computer system is studied and investigated. An analytic queueing model is derived for one cluster of the architecture. These results were validated by developing a discrete-event simulation model written in SIMSCRIPT II.5 simulation language. The simulator uses real values for its input parameters, collected by using one processor module and a logic analyzer. The analytical performance results closely match the simulation model performance results. The primary performance index used in the modeling is the speedup. Other performance measures can easily be derived from the speedup.     

Sequence-preserving parallel IP lookup using multiple SRAM-based pipelines

SRAM (static random access memory)-based pipelined algorithmic solutions have become competitive alternatives to TCAMs (ternary content addressable memories) for high-throughput IP lookup. Multiple pipelines can be utilized in parallel to improve the throughput further. However, several challenges must be addressed to make such solutions feasible. First, the memory distribution over different pipelines, as well as across different stages of each pipeline, must be balanced. Second, the traffic among these pipelines should be balanced. Third, the intra-flow packet order (i.e. the sequence) must be preserved. In this paper, we propose a parallel SRAM-based multi-pipeline architecture for IP lookup. A two-level mapping scheme is developed to balance the memory requirement among the pipelines as well as across the stages in each pipeline. To balance the traffic, we propose an early caching scheme to exploit the data locality inherent in the architecture. Our technique uses neither a large reorder buffer nor complex reorder logic. Instead, a flow-aware queuing scheme exploiting the flow information is used to maintain the intra-flow sequence. Extensive simulation using real-life traffic traces shows that the proposed architecture with 8 pipelines can achieve a throughput of up to 10 billion packets per second, i.e. 3.2 Tbps for minimum size (40 bytes) packets, while preserving intra-flow packet order.     

High speed flexible fuzzy hardware for fuzzy information processing

In this paper, we present a system called KAFA (Kaist Fuzzy Accelerator) which provides various fuzzy inference methods and fuzzy set operations. The basic idea of this study is to develop a more general purpose hardware system. The architecture has SIMD structure, which consists of two parts; a system control unit (main controller), and an arithmetic unit (fuzzy processing element (FPE)). Microinstruction codes are defined and any fuzzy operation can be programmed by using these microinstructions. Each FPE has the maximum speed of 10 M FLOPS. As the KAFA contains 128 FPE's, if a fuzzy set consists of 128 elements, we achieve the peak performance of 10 M FSOPS (fuzzy set operation per second) under 10 MHz clock frequency. This system also includes the parallel algorithms for defuzzification on the SIMD mode architecture using KAFA network. The prototype of the proposed architecture was developed with the FPGA chips. The speed of the KAFA holds promise for the development of the new fuzzy application system such as automatic control, fuzzy expert systems, real time systems and fuzzy databases     

Decidable metric logics

The common metric temporal logic for continuous time were shown to be insufficient, when it was proved that they cannot express a modality suggested by Pnueli. Moreover no finite temporal logic can express all the natural generalizations of this modality. It followed that if we look for an optimal decidable metric logic we must accept infinitely many modalities, or adopt a different formalism.Here we identify a fragment of the second order monadic logic of order with the “+1” function, that expresses all the Pnueli modalities and much more. Its main advantage over the temporal logics is that it enables us to say not just that within prescribed time there is a point where some punctual event will occur, but also that within prescribed time some process that starts now (or that started before, or that will start soon) will terminate. We prove that this logic is decidable with respect to satisfiability and validity, over continuous time. The proof depends heavily on the theory of compositionality. In particular every temporal logic that has truth tables in this logic is automatically decidable. We extend this result by proving that any temporal logic, that has all its modalities defined by means more general than truth tables, in a logic stronger than the one just described, has a decidable satisfiability problem. We suggest that this monadic logic can be the framework in which temporal logics can be safely defined, with the guarantee that their satisfiability problem is decidable.     

GEAMAS: A Generic Architecture for Agent-Oriented Simulations of Complex Processes

This paper's object is to present the results of the GEAMAS project which aims at modeling and simulating natural complex systems. GEAMAS is a generic architecture of agents used to study the behavior emergence in such systems. It is a multiagent program meant to develop simulation applications. Modeling complex systems requires to reduce, to organize the system complexity and to describe suitable components. Complexity of the system can then be tackled with an agent-oriented approach, where interactions lead to a global behavior. This approach helps in understanding how non-determinist behavior can emerge from interactions between agents, which is near of self-organized criticality used to explain natural phenomena. In the Applied Artificial Intelligence context, this paper presents an agent software architecture using a model of agent. This architecture is composed of three abstract levels over which the complexity is distributed and reduced. The architecture is implemented in ReActalk, an open agent-oriented development tool, which was developed on top of Smalltalk-80. To illustrate our purpose and to validate the architecture, a simulation program to help in predicting volcanic eruptions was investigated. This program was run over a period of one year and has given many satisfying results unattainable up to there with more classical approaches.     

Multimodal registration of visible,SWIR and LWIR images in a distributed smart camera system

We present a multimodal registration algorithm between images in the visible, short-wave infrared and long-wave infrared spectra. The algorithm works with two reference-objective image pairs and operates in two stages: (1) A calibration phase between static frames to estimate the transformation parameters using histogram of oriented gradients and the Chi-square distance; (2) a frame-by-frame mapping with these parameters using a projective transformation and a bilinear interpolation to map the objective video stream to the coordinate system of the reference video stream. We present a distributed heterogeneous architecture that combines a programmable processor core and a custom hardware accelerator for each node. The software performs the calibration phase, whereas the hardware computes the frame-by-frame mapping. We implemented our design using a Xilinx Zynq XC7Z020 system-on-a-chip for each node. The prototype uses 2.38W of power, 25% of the logic resources and 65% of the available on-chip memory per node. Running at 100MHz, the core can register 640  ×  512-pixel frames in 4ms after initial calibration, which allows our module to operate at up to 250 frames per second.     

多播3-Omega交换网的设计思想

阐述了具有最佳硬件复杂度且可无阻地在输入/输出间传输任意多播信号的多播3-Omega网的设计思想，设计理念可表述为“置换-复制-置换”，组成形式为“Omega-1+Omega+Omega-1”。它具有O(nlogn)的硬件代价，存储空间和时间复杂度均为O(nlogn)，连接建立时间为(logn)，传输延迟O(logn)，符合Shannon的硬件代价极限标准，具有良好的可实现性。     

用于实验室调试的数字量测试平台设计

现场模拟系统是针对管道自动化系统集成测试而设计的,它为实验室调试提供了一个仿真的现场环境,可以对自动化系统的多个工艺控制流程进行测试,完成现场难以完成的控制逻辑测试,提高控制系统的可靠性及控制逻辑准确性,也可以用于对员工的培训,使员工的成长更迅速.现场模拟系统一共由数字量模拟系统、模拟量仿真系统及通讯调试设备三部分构成...     

基于JavaBeans的Web考试系统的设计与实现

描述了web考试系统的工作流程。提出用JavaBeans技术实现Web考试系统，以使服务器端的复杂业务逻辑与客户端表现逻辑分离。采用Java Servlet作为控制器，将试卷抽取等业务逻辑封装在JavaBeans组件中，用JSP完成动态页面的显示及与Web服务器的交互，给出了JavaBeans的实现。     

Mediator approach to direct workflow simulation

This paper presents a direct workflow simulation method with which the future enactment service processes of a BPM system can be simulated directly (i.e., without a model conversion). The proposed method may easily be implemented on a commercial BPM system by plugging in a couple of software modules (no internal modification of the BPM system is required). Previous researches on workflow simulation relied mostly on conversion methods in which process definition models (PDMs) are converted to simulation models and the simulation is performed by a separate simulator. More recently, a direct workflow simulation method based on the concept of listener was proposed. However, with the listener approach, (1) some internal modification of the BPM system is required, (2) PDMs have to be modified slightly, and (3) reliable simulation is not guaranteed. The direct workflow simulation approach proposed in this paper, which we call the mediator approach, is free of these shortcomings. Moreover, the mediator approach is suitable for workflow simulation involving multiple BPM systems. In a ‘direct’ workflow simulation, (1) the work-list handler of each participant is replaced by a participant simulator, (2) simulation is carried out by the workflow engine of the BPM system, and (3) a software module called synchronization manager (mediator or listener) handles time synchronization during simulation. In this paper, the architecture and detailed logic of the mediator are described as DEVS models. The behaviors of participant simulators are also described as DEVS models. The proposed workflow simulation method has been implemented on a commercial BPM system as well as on an academic BPM system, and an illustrative workflow simulation example is provided.     

A new methodology for deriving the rule-base of a fuzzy logic controller with a new internal structure

In this study, a fuzzy logic controller is developed using a new methodology for designing its rule-base. This controller consists of two rule-base blocks and a logical switch in between. The rule-base blocks admit two inputs one of which is newly devised and called “normalized acceleration” and the other one is the classical “error”. The newly devised input is derived using the first and the second order derivatives of the error and it gives a relative value about the “fastness” or “slowness” of the system response. A comparative performance analysis has been made through the simulation results of the MacVicar-Whelan controller and the proposed fuzzy logic controller on a marginally stable system. The robustness and effectiveness of the new fuzzy logic controller over the typical MacVicar-Whelan controller has also been illustrated by simulations done on a system under various disturbances and time delays.     

A novel architecture design for VLSI implementation of integer DCT in HEVC standard

This paper presents novel hardware of a unified architecture to compute the 4?×?4, 8?×?8, 16?×?16 and 32?×?32 efficient two dimensional (2-D) integer DCT using one block 1-D DCT for the HEVC standard with less complexity and material design. As HEVC large transforms suffer from the huge number of computations especially multiplications, this paper presents a proposition of a modified algorithm reducing the computational complexity. The goal is to ensure the maximum circuit reuse during the computation while keeping the same quality of encoded videos. The hardware architecture is described in VHDL language and synthesized on Altera FPGA. The hardware architecture throughput reaches a processing rate up to 52 million of pixels per second at 90 MHz frequency clock. An IP core is presented using the embedded video system on a programmable chip (SoPC) for implementation and validation of the proposed design. Finally, the proposed architecture has significant advantages in terms of hardware cost and improved performance compared to related work existing in the literature. This architecture can be used in ultra-high definition real-time TV coding (UHD) applications.

     

WebCCTV中的流量控制设计与实现

本文首先介绍了WebCCTV监控系统的逻辑结构，并针对系统中的数据传输机制进行了分析；然后提出了基于分组对技术的复杂速率控制机制，并说明了相应的系统结构设计；最后给出了算法的仿真和分析。