WLAN应用的CMOS低噪声放大器设计

采用TSMC0.25μmCMOS工艺设计了一个IEEE802.11a标准无线局域网(WLAN)应用的5.8GHz差分低噪声放大器(LNA)。阐述了LNA的噪声优化和设计过程。采用Agilent ADS仿真,结果显示:2.5V工作电压下,LNA增益为14.6dB,噪声系数为1.72dB,1dB压缩点为-10.2dBm,功耗16.5mW。     

2.4GHz低噪声放大器的全芯片ESD保护设计

设计并流片验证了一种0.18μmRFCMOS工艺的2.4GHz低噪声放大器的全芯片静电放电(ESD)保护方案。对于射频(RF)I/O口的ESD防护,主要对比了二极管、可控硅(SCR)以及不同版图的互补型SCR,经流片与测试,发现岛屿状互补型SCR对I/O端口具有很好的ESD防护综合性能。对于电源口的ESD防护,主要研究了不同触发方式的ESD保护结构,结果表明,RCMOS触发SCR结构(RCMOS-SCR)具有良好的ESD鲁棒性和开启速度。基于上述结构的全芯片ESD保护设计,RF I/O口采用岛屿状布局的互补SCR结构的ESD防护设计,该ESD防护电路引入0.16dB的噪声系数和176fF的寄生电容,在人体模型(HBM)下防护能力可达6kV;电源口采用了RCMOS-SCR,实现了5kV HBM的ESD保护能力,该设计方案已经在有关企业得到应用。     

应用于导航系统的低噪声放大器设计

设计了一个应用于1.57GHz导航系统的高性能的低噪声放大器,电路设计基于SMICRF 0.18umCMOS工艺完成,利用Cadence进行了电路设计和仿真。采用了单端共源共栅结构,该结构较为简单,所用器件较少,便于集成。通过调整输入输出匹配等电路结构显著提升了电路的性能,仿真结果显示17.8dB的增益,0.42dB的噪声系数,8.7dBm的输入三阶交调点。     

宽带低噪声放大器与ESD防护的协同设计

基于0.18 μm CMOS工艺,介绍了一种UHF频段低噪声放大器(LNA)与静电放电(ESD)保护器件的协同设计和电路仿真方法.采用传输线脉冲测试系统,测得ESD二极管的正向热失效击穿电流为4.28 A,等效于人体模型5.6 kV;反向热失效击穿电流为0.2A,等效于人体模型500 V.通过仿真,分析了ESD二极管的电阻、电容特性,给出了其在LNA正常工作情况下的等效电路;结合LNA电路仿真结果,比较了二极管寄生效应对LNA阻抗匹配、增益、噪声系数和线性度等指标的影响,验证了等效电路的正确性.     

宽频带低噪声放大器设计

采用Lange耦合器的宽频带特性设计L／S波段平衡式低噪声放大器电路,并通过仿真设计软件对放大器的工作频带、噪声系数、增益及输入、输出驻波比等几个重要指标进行优化。最后设计的放大器在1．2～2．5GHz频率范围内增益为33～35dB,噪声系数不大于1dB,输入输出驻波比小于1．5,达到了预定的技术指标要求,性能良好。     

0.18-um CMOS 3.1-10．6GHz超宽带低噪声放大器设计

介绍了一种基于0．18-um CMOS工艺、适用于超宽带无线通信系统接收前端的低噪声放大器。在3．1～10．6GHz的频带范围内对它仿真获得如下结果：最高增益12dB；增益波动小于2dB；输入端口反射系数S11小于-10dB；输出端口反射系数S22小于-15dB；噪声系数NF小于4．6dB。采用1．5V电源供电，功耗为10．5mW。与近期公开发表的超宽带低噪声放大器仿真结果相比较，本电路结构具有工作带宽大、功耗低、输入匹配电路简单的优点。     

用于无线传感网络低功耗亚阈值CMOS低噪声放大器设计

设计一种工作在亚阈值区的低功耗CMOS低噪声放大器(LNA),用于无线传感网络.为了满足低功耗和高增益,设计使用共源共栅(cascode)结构并利用UMC 65nm工艺库进行仿真分析.仿真结果表明,在780MHz中心频率下,电路的增益大约34 dB,功耗仅为55μW,电源电压为1.2V.     

用于物联网双频段低功耗CMOS低噪声放大器设计

设计一种用于物联网双频段的低功耗CMOS低噪声放大器(LNA).为了满足双频段和高增益,设计使用共源共栅(Cascode)结构并利用TSMC 0.18um工艺库进行仿真分析.仿真结果表明,在780MHz和433MHz中心频率下,电路的S11均小于-20dB和S21均大于20dB,并且具有好的稳定性.     

0.18 μm CMOS射频低噪声放大器设计

基于TSMC 0.18μm RFCMOS工艺,设计了一种工作于2.4 GHz频段的低噪声放大器。电路采用Cascode结构,为整个电路提供较高的增益,然后进行了阻抗匹配和噪声系数的性能分析,最后利用ADS2009对其进行了模拟优化。最后仿真结果显示。该放大器的正向功率增益为14 d B,噪声系数小于2 d B,1 d B压缩点为-13 d Bm,功耗为7.8 m W,具有良好的综合性能指标。     

基于噪声抵消技术的宽带低噪声放大器设计

采用0.18μm CMOS工艺,针对DMB-T/H标准数字电视调谐器应用,设计了一个基于噪声抵消技术的宽带低噪声放大器.详细分析了噪声抵消技术的原理,给出了宽带低噪声放大器的设计过程.仿真结果表明,在48～862 MHz频率范围内输入输出反射系数均小于-20 dB,噪声系数低于3 dB,增益大于17 dB,1 dB压缩点为-6dBm.在1.8V电压下,电路功耗为10.8mW.     

A 1 V switchable CMOS LNA for 802.11A/B WLAN applications

A new dual-band, 2.4 and 5.2 GHz, combined LNA, which can operate at 1 V supply only, for WLAN application is presented. The switched transistor technique is used in the LNA. It could match the input port in two frequency bands and reduce one on-chip spiral inductor usage compared with [1, 2]. Theoretical analysis and transistor level simulation results using 0.18 μm CMOS process from Chartered Semiconductor are presented to demonstrate this idea. Wang-Chi Cheng received his B.Eng., M.Phil., and Ph.D. degrees in Electronic Engineering of the Chinese University of Hong Kong (CUHK) in 1999, 2001 and 2004. His research achievements during M.Phil. and Ph.D. studies were in the field of low voltage receiver front-end circuits design with CMOS technology. He joined the Electrical and Electronic Engineering department of Nanyang Technological University (NTU), Singapore, in May 2005 as a Research Fellow. Now, he is a Senior Engineer in charge of the UWB transceiver IC design in Hong Kong Applied Science and Technology Research Institute (ASTRI). His current research interests include 802.11 A/B WLAN and UWB transceiver design. He is also a paper reviewer of the IEEE Microwave and Wireless Components Letters. Jian-Guo Ma received his B.Sc. and M.Sc. in 1982 and 1988 respectively with honors from Lanzhou university of Chain, and Doctoral Degree in Engineering from Gerhard-Mercator University of Germany in 1996. From Jan. 1982 to March 1991, he has worked with Lanzhou university of China on RF & Microwave Engineering. Before he joined Nanyang Technological University in 1997, he was with Technical University of Nova Scotia, Canada. Now, he is a Professor of the University of Electronic Science and Technology of China. His research interests are: RFIC designs for wireless applications; RF characterization and modeling of semiconductor devices; RF interconnects and packaging; SoC and Applications; EMC/EMI in RFICs. He has published more than 150 technical papers and two books in above mentioned areas. He holds 6 patents in CMOS RFICs. He is now Associate Editor for IEEE Microwave and Wireless Components Letters. Kiat-Seng Yeo received his B.E. (Hons.) (Elect) in 1993, and Ph.D. (Elect. Eng.) in 1996 both from Nanyang Technological University, Singapore. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore as a Lecturer in 1996, and became an Assistant Professor and an Associate Professor in 1999 and 2002, respectively. Professor Yeo provides consulting to statutory boards and multinational corporations in the areas of semiconductor devices and electronic circuit design. He has been extensively involved in the modeling and fabrication of small MOS/Bipolar integrated technologies for the last ten years. His research interests also include the design of new circuits and systems (based on scaled technologies) for low-voltage low-power applications; radio frequency integrated circuit (RF IC) design; integrated circuit design of BiCMOS/CMOS multiple-valued logic circuits, domino logic, and memories; and device characterization of deep submicrometer MOSFETs. Manh-Anh Do obtained his B.E. (Hons) (Elect.) in 1973, and Ph.D. (Elect. Eng.) in 1977 both from University of Canterbury, New Zealand. Between 1977 and 1989, he held various positions including: R & D engineer and production manager at Radio Engineering Ltd., research scientist at Fisheries Research Centre, New Zealand, and senior lecturer at National University of Singapore. He joined the School of Electrical and Electronic Engineering, Nanyang Technological University (NTU), Singapore as a senior lecturer in 1989, and obtained the Associate Professorship in 1996 and the Professorship in 2001. He has been a consultant for many projects in the Singapore electronic industry, and was the principal consultant for the design, testing and implementation of the $200 million Electronic Road Pricing (ERP) island-wide project in Singapore, from 1990 to 2001. His current research is on digital and mobile communications, RF IC design, mixed-signal circuits and intelligent transport systems. Before that, he specialsed in sonar designing, biomedical engineering and signal processing. Since 1995, he has been Head of Division of Circuits and Systems, School of EEE, NTU. He is a Fellow of IEE, UK, a Chartered Engineer (UK) and a Professional Engineer (Singapore).     

应用于2.4GHz无线传感网的带ESD保护CMOS低噪声放大器的设计与优化

本文给出一种新的带ESD保护源极电感负反馈低噪声放大器优化方法,可以实现在功耗受限条件下的噪声和输入同时匹配,并给出了输入阻抗和噪声参数的分析。采用该方法设计并优化了一个基于0.18-μm RF CMOS工艺、应用于无线传感网的2.4GHz低噪声放大器。测试结果表明,低噪声放大器的噪声系数为1.69dB,功率增益为15.2dB,输入1dB压缩点为-8dBm,输入三阶截点为1dBm,1.8V电源电压下的工作电流为4mA。     

Design and optimization of CMOS LNA with ESD protection for 2.4 GHz WSN application

A new optimization method of a source inductive degenerated low noise amplifier(LNA) with electrostatic discharge protection is proposed.It can achieve power-constrained simultaneous noise and input matching. An analysis of the input impedance and the noise parameters is also given.Based on the developed method,a 2.4 GHz LNA for wireless sensor network application is designed and optimized using 0.18-μm RF CMOS technology. The measured results show that the LNA achieves a noise figure of 1.59 dB,a power gain of 14.12 dB, an input 1 dB compression point of-8 dBm and an input third-order intercept point of 1 dBm.The DC current is 4 mA under a supply of 1.8 V.     

应用于802.11a的5.7GHz CMOS LNA设计

使用0.18μm CMOS工艺设计应用于802.11a WLAN的U-NII高频段5.7GHz的LNA.首先选取LNA结构,推导出噪声模型,然后选取在固定功率消耗下最小噪声系数对应的晶体管尺寸,再进行输入输出阻抗匹配和电路调整优化.在使用Bond Wire不加Pad时提供-22.014dB S11,-44.902dB S22,15.063dB S21,-39.44dB S12,2.453dB/2.592dB的噪声系数(NF),-4.1915dBm的三阶互调输入点(IIP3),-15.6dBm的功率1dB压缩点(P1dB)和10mW的功率消耗(Pd).完全考虑Bond Wire和Pad效应的性能参数也已经给出,但噪声系数恶化为3.21/3.23dB,S参数在电路调整优化之后变化不大,整体性能比较突出.     

基于802.11a协议的无线局域网低噪声放大器和改进的有源双平衡混频器

提出了采用0.18μm CMOS工艺,应用于802.11a协议的无线局域网接受机的低噪声放大器和改进的有源双平衡混频器的一些简单设计概念。通过在5.8 GHz上采用1.8 V供电所得到的仿真结果,低噪声放大器转换电压增益,输入反射系数,输出反射系数以及噪声系数分别为14.8 dB,-20.8 dB,-23.1 dB和1.38 dB。其功率损耗为26.3 mW。设计版图面积为0.9 mm×0.67 mm。混频器的射频频率,本振频率和中频频率分别为5.8 GHz,4.6 GHz和1.2 GHz。在5.8 GHz上,混频器的传输增益,单边带噪声系数（SSB NF）,1 dB压缩点,输入3阶截点（IIP3）以及功率损耗分别为-2.4 dB,12.1 dB,3.68 dBm,12.78 dBm和22.3 mW。设计版图面积为1.4 mm×1.1 mm。     

A CMOS 4.1 GHz two-stage cascode LNA with ESD protection

A 4.1 GHz two-stage cascode Low-Noise Amplifier (LNA) with Electro-Static Discharge (ESD) protection is presented in this paper. The LNA has been optimized using ESD and LNA co-design methodology to achieve a good performance. Post-layout simulation results exhibit a forward gain (S21) of about 21 dB, a reverse isolation (S12) of less than –18 dB, an input return loss (S11) of less than –16 dB, and an output return loss (S22) of less than –17 dB. Moreover, the Noise Figure (NF) is 2.6 dB. This design is implemented in TSMC0.18μm RF CMOS technology and the die area is 0.9 mm 0.9 mm.     

CMOS集成电路的ESD设计技术

首先论述了CMOS集成电路ESD保护的必要性 ,接着介绍了CMOS集成电路ESD保护的各种设计技术 ,包括电流分流技术、电压箝位技术、电流均衡技术、ESD设计规则、ESD注入掩膜等。采用适当的ESD保护技术 ,0 8μmCMOS集成电路的ESD能力可以达到 30 0 0V。     

基于CMOS工艺的全芯片ESD保护电路设计

介绍了几种常用ESD保护器件的特点和工作原理,通过分析各种ESD放电情况,对如何选择ESD保护器件,以及如何设计静电泄放通路进行了深入研究,提出了全芯片ESD保护电路设计方案,并在XFAB 0.6 μm CMOS工艺上设计了测试芯片.测试结果表明,芯片的ESD失效电压达到5 kV.     

带有ESD保护,900MHz/2.4 GHz Dual-BandCMOS LNA的设计

设计了一个可以同时工作在900 MHz和2.4 GHz的双频带(Dual-Band)低噪声放大器(LNA).相对于使用并行(parallel)结构LNA的双频带解决方案,同时工作(concurrent)结构的双频带LNA更能节省面积和减少功耗.此LNA在900MHz和2.4 GHz两频带同时提供窄带增益和良好匹配.该双频带LNA使用TSMC 0.25 μm 1P5M RF CMOS工艺.工作在900MHz时,电压增益、噪声系数(Noise Figure)分别是21 dB、2.9 dB;工作在2.4 GHz时,电压增益、噪声系数分别是25dB、2.8 dB,在电源电压为2.5 V时,该LNA的功耗为12.5mW,面积为1.1mm×0.9 mm.使用新颖的静电防护(ESD)结构使得在外围PAD上的保护二极管面积仅为8 μm×8 μm时,静电防护能力可达2 kV(人体模型)