基于EIT技术的微区薄层电阻测试系统研究

分析了各种半导体材料电阻率测量方法的优缺点及适用性,利用电阻抗成像技术(EIT),探究了一种用来检测Si片内微区薄层电阻率均匀性的无接触测试技术.实现这种测试技术的硬件电路系统主要由激励模块恒流源、驱动模块多路模拟开关、信号处理模块前置放大电路、A/D转换器件和DSP(数字信号处理器)芯片、计算机等构成.分别介绍了各模块的构成与功能,并略述了用一种图像重建算法等位线反投影法进行阻抗分布图像的重建.     

四探针技术测量薄层电阻的原理及应用

对四探针技术测试薄层电阻的原理进行了综述,重点分析了常规直线四探针法、改进范德堡法和斜置式方形Rymaszewski法的测试原理,并应用斜置式Rymaszewski法研制成新型的四探针测试仪,利用该仪器对样品进行了微区(300μm×300μm)薄层电阻测量,做出了样品的电阻率等值线图,为提高晶锭的质量提供了重要参考.     

微处理器在微区薄层电阻测试Mapping技术中的应用

本文利用微区薄层电阻测试的一种斜置四探针新方法，将扩散微区薄层电阻测试结果绘成全乍的灰度图，这种微区薄层电阻测试Ｍａｐｐｉｎｇ技术十分有利于评价材料的质量。在测试过程中应用微处理器，可立即数字显示相应的测量电压及微区的薄层电阻，加快了计算速度并有利于控制探针的合适位置。     

微区电阻测试方法及新测试仪研制

文章对国内外开展微区薄层电阻测试的方法进行了综述，特别对改进范德堡四探针技术方法的测试原理、测试过程与测试结果进行了论述与分析，对微区电阻测试方法的进一步发展提出了一种可操作的方法，并研制出新型四探针测试样机。     

微处理器在微区薄层电阻测试Mapping技术中的应用

利用微区薄层电阻测试的一种斜置四探针新方法，将扩散微区薄层电阻测试结果绘成全片的灰度图，这种Ｍａｐｐｉｎｇ技术十分有利于评价材料的质量，在测试过程中应生处理器，可立即数字显示相应的测量电压及微区的薄层电阻，加快计算速度并有利于控制探针的合适位置。     

无测试图形薄层电阻测试仪及探针定位

研制出检测ULSI芯片的薄层电阻测试仪,可用于测试无图形样片电阻率的均匀性,用斜置的方形四探针法,经显微镜、摄像头及通信口接入计算机,从计算机显示器观察,用程序及伺服电机控制平台和探针移动,使探针处于规定的位置,实现自动调整、测试;对测试系统中的探针游移造成的定位误差进行分析,推导出探针游移产生误差的计算公式,绘制了理论及实测误差分布图;测出无图形100mm样品电阻率,并绘制成等值线Mapping图.     

无测试图形薄层电阻测试仪及探针定位

研制出检测U L SI芯片的薄层电阻测试仪,可用于测试无图形样片电阻率的均匀性,用斜置的方形四探针法,经显微镜、摄像头及通信口接入计算机,从计算机显示器观察,用程序及伺服电机控制平台和探针移动,使探针处于规定的位置,实现自动调整、测试;对测试系统中的探针游移造成的定位误差进行分析,推导出探针游移产生误差的计算公式,绘制了理论及实测误差分布图;测出无图形10 0 m m样品电阻率,并绘制成等值线Mapping图.     

基于统计反演的硅片微区电阻率测试方法

提出了一种基于统计反演重建电阻率分布图像的硅片电阻率测试方法，该方法采用马尔科夫链蒙特卡洛(MCMC)方法求解电阻抗成像技术(EIT)的逆问题，可以避免确定性方法中迭代误差和分辨率低的问题。建立了一种基于MCMC方法的电阻率分布图像重建算法，搭建了电压数据采集系统以测量边缘电压。对比MCMC算法重建的硅片微区电阻率分布图像与4D-333A测试仪的测量结果，二者的电阻率分布情况呈现出相同的分布趋势。将采用MCMC算法得出的256个单元的数值与采用其他重建方法得出的数值、真实的电阻率进行对比，发现MCMC算法得到的数值与真实数值最接近的单元数最多，为88个，比其他重建方法更为准确。     

薄层电阻测试Mapping技术

利用改进的范德堡法微区薄层电阻测试探针技术对n-Si片上的硼扩散图形进行薄层电阻的测量，并用发度表示其分布，可得到薄层电阻的不均匀度及平均值．这种所谓Mapping技术更有利于评价材料质量．     

微区薄层电阻四探针测试仪及其应用

用斜置的四探针方法 ,依靠显微镜观察 ,将针尖置于微区图形的四个角区 ,用改进的范德堡公式可以得到微区的薄层电阻。文中对测准条件作了分析。并用该仪器测定了硼扩散片的薄层电阻分布。在测试过程中应用微处理器 ,加快了计算速度     

High resistivity measurement of SiC wafers using different techniques

To establish fast, nondestructive, and inexpensive methods for resistivity measurements of SiC wafers, different resistivity-measurement techniques were tested for characterization of semi-insulating SiC wafers, namely, the four-point probe method with removable graphite contacts, the van der Pauw method with annealed metal and diffused contacts, the current-voltage (I-V) technique, and the contactless resistivity-measurement method. Comparison of different techniques is presented. The resistivity values of the semi-insulating SiC wafer measured using different techniques agree fairly well. As a result, application of removable graphite contacts is proposed for fast and nondestructive resistivity measurement of SiC wafers using the four-point probe method. High-temperature van der Pauw and room-temperature Hall characterization for the tested semi-insulating SiC wafer was also obtained and reported in this work.     

Limitations on the range of measurements of sheet resistivity of shallow diffused layers for profiling by the four-point-probe technique

It is found that the standard four-point probe resistivity measurement and stripping technique used for measuring impurity profile in diffused semiconductor layers can provide reliable information only if certain limitations are carefully observed. To get the actual surface concentration for profiling, it has been found necessary to predetermine the appropriate range of current and voltage. Approximate ranges for studying phosphorus and boron in silicon are reported in this paper. The phosphorus profile obtained by this technique by successive measurement of sheet resistivity after anodic oxidation and stripping distinctly shows a kink and tail structure obtained without annealing.     

四探针Rymaszewski法电阻率测量新型电路

为了适应半导体生产工艺发展的要求,我们开发了一种利用改进的Rymaszewski法进行四探针硅片电阻率测量的单片机电路。它主要包括恒流源和电压测量电路两部分。它不仅可以显示恒流源电流以便在其发生变化时进行调整,而且可以方便地实现四根探针分别经过四次轮换供给电流和测量电压,进而提高测量结果的精确性。     

缓冲层厚度对透明导电薄膜ZnO:Zr性能的影响

利用直流磁控溅射法在有ZnO:Zr缓冲层的水冷玻璃衬底上成功制备出了ZnO:Zr透明导电薄膜,缓冲层的厚度介于35～208 nm.利用XRD、SEM、四探针测试仪和紫外-可见分光光度计研究ZnO:Zr薄膜的结构、形貌、电光性能.结果表明,薄膜的颗粒尺寸和电阻率对缓冲层厚度具有较强的依赖性.当缓冲层厚度从35 nm增加到103 nm时,薄膜的颗粒尺寸增大,电阻率减小.而当缓冲层厚度从103 nm增加到208 nm时,薄膜的颗粒尺寸减小,电阻率增大.当缓冲厚度为103 nm时,薄膜的电阻率最小为2.96×10-3 Ω·cm,远小于没有缓冲层时的12.9×10-3 Ω·cm.实验结果表明,在沉积薄膜之前先沉积一层适当的缓冲层是提高ZnO:Zr薄膜质量的一种有效方法.     

Prestressed Ceramic Coatings for Enhanced Reliability of Silicon Wafer Fracture Strength

The objective of this paper is to investigate thin, solid, prestressed ceramic films as a means of enhancing the reliability of silicon semiconductor wafers stressed in bending. To characterize the effect of thin films on strength, one-micrometer ceramic films were deposited on wafers using plasma-enhanced chemical-vapor deposition. The modulus of rupture (MOR) of the coated wafers was determined from four-point bend testing of coated samples. Adhesion testing of the coated wafers primarily showed cohesive rather than adhesive failure. A series of residual stresses was introduced into the coating-silicon interface and the MOR was determined. The results showed that for a thin brittle coating (1 mum) on a silicon wafer (635 mum), the minimal shear stress at the surface led to dominance of the residual stress over intrinsic coating strength as the critical parameter affecting failure. A correlation between MOR and residual stress was established.     

碲化铅薄膜电学特性的研究

用真空蒸镀法制备了Pb49Te51薄膜,并对薄膜的显微结构、导电类型和电阻率等电学特性及热处理对薄膜性能的影响进行了研究。结果表明:热处理对薄膜结构和性能影响很大,热处理后薄膜呈铜黄色,晶粒有明显取向,其形状为片状,且晶粒尺寸变大为300~400nm;薄膜为p型半导体薄膜,其电阻率4.624×10–2Ω.cm比晶体材料12.410×10–2Ω.cm大。     

掺铝ZnO透明导电薄膜的制备及光电性能研究

采用RF磁控溅射法制备了掺铝ZnO(AZO)透明导电薄膜,用X射线衍射仪、分光光度计和四探针仪等,研究了沉积温度对薄膜晶体结构和光电性能的影响。结果表明,AZO薄膜为六方纤锌矿结构的多晶膜,具有(002)择优取向。沉积温度对薄膜的择优取向程度、晶粒尺寸、透射率和导电性能等具有明显的影响。当沉积温度为400℃时,AZO薄膜最大晶粒尺寸为37.21nm、可见光范围平均透射率为85.5%、优良指数为1.30×10-2?-1。     

Synthesis of low resistivity complex oxides on MgO using Pt as buffer layer

Highly crystalline SrRuO₃ (SRO) and La_0.5Sr_0.5CoO₃ (LSCO) thin films were deposited on (100) Pt/ MgO by pulsed laser deposition. The films were mainly (001) textured normal to the substrate surface with a high degree of in-plane orientation with respect to the substrate’s major axes. These films were characterized using x-ray diffraction, Rutherford backscattering, four-point probe resistivity measurement, and transmission electron microscopy. The room temperature resistivity for LSCO and SRO films on Pt/MgO was found to be ∼35 and ∼40 μΩ-cm, respectively. An ion beam minimum channeling yield of ∼43% and ∼33% was obtained for LSCO and SRO films, respectively. The interface between Pt and oxide was found to be smooth and free from any interfacial diffusion. This result showed that high-quality low resistivity oxide thin films can be deposited on Pt.     

基底温度对直流磁控溅射ITO透明导电薄膜性能的影响

用直流磁控溅射法制备透明导电锡掺杂氧化铟(ITO)薄膜,靶材为ITO陶瓷靶,组分为m(In2O3):m(SnO2)=9:1.运用分光光度计,四探针测试仪研究了基底温度对薄膜透过率、电阻率的影响,并用X射线衍射(XRD)仪对薄膜进行结构分析.计算了晶面间距和晶粒尺寸,分析了薄膜的力学性质.实验结果表明,在实验设备条件下,直流磁控溅射ITO陶瓷靶制备ITO薄膜时,适当的基底温度(200℃)能在保证薄膜85%以上高可见光透过率下,获得最低的电阻率,即基底温度有个最佳值.薄膜的结晶度随着基底温度的提高而提高.     

Enhancement of Oxidation Resistance and Electrical Properties of Indium-Doped Copper Thin Films

Copper thin films with high conductivity and good resistance to electromigration can be used in advanced electronic devices. However, the poor corrosion resistance of copper must be overcome. This work elucidates the possibility of using a self-forming passivation layer to prevent copper oxidation in lightly indium-doped copper thin films deposited directly on glass substrates and annealed under various oxygen atmospheres. The resistivity of the studied film declined gradually as the film was annealed at an elevated temperature because of the grain growth of the Cu film and the precipitation of indium from the In-doped Cu thin film, as revealed by X-ray diffraction, four-point probe measurements, and transmission electron microscopy. A copper film with high indium content exhibited superior passivation when the film was annealed in an oxygen-rich ambient, but it exhibited high resistivity because of its high indium content. The electrical and passivation properties demonstrated that indium is a promising alloying element for use in copper films for future metallization structures and thin-film transistors.