Design of CMOS checkers with improved testability of bridging and transistor stuck-on faults

This work presents a design technique for CMOS static and dynamic checkers (to be used in self-checking circuits), that allows the detection of all internal single transistor stuck-on and bridging faults causing unacceptable degradations of the circuit dynamic performance (but not logical errors). Such a technique exploits simple voltage detector circuits to make sure that the intermediate faulty voltages inevitably produced by the faults of interest are always propagated at the checker output as logic errors.With the use of our technique, the main disadvantages of static checkers, so far preventing their use in practical applications, are overcome.The method has been applied to the particular case of two-rail (static as well as dynamic) checkers and its validity has been verified by means of electrical level simulations.     

组合电路桥接故障诊断的测试生成及优化

在利用划分等价类的方法来诊断组合电路中桥接故障的基础上,本文提出了一种基于门特性的IDDQ测试集生成算法及对测试集排序筛选的优化方法.实验结果表明,将此方法应用于组合电路桥接故障的诊断可缩减测试集的大小,提高诊断的故障覆盖率.     

Fault simulation for general FCMOS ICs

This work presents a technique to correctly deal with non-stuck-at faults in FCMOS circuits making use of complex macrogates. This method can be applied to any gate-level fault simulator providing, for each line of the circuit, the observability status that is directly related to that of individual devices in the actual macrogate implementation. Conductance conflicts are correctly solved to detect bridgings and transistors stuck-on. Fault coverage results are presented and discussed for two typical FCMOS circuits. Results obtained on all ISCAS benchmarks show that the time required for the fault simulation of CMOS faults is comparable to that of stuck-ats.     

薄膜SOI／CMOS的SPICE电路模拟

鉴于ＳＰＩＣＥ是目前世界上广泛采用的通用电路模拟程序，具具有可扩展模型的灵活性，我们通过修改ＳＰＩＣＥ源程序把新器件模型－－ＳＯＩＭＯＳＦＥＴ模型移植入ＳＰＩＣＥ中，通过我们的模拟工作，证实了我们模型的正确性和电路实用性，分析了器件参数对ＳＯＩ／ＣＭＯＳ电路速率的影响，这些结论可以很好地指导电路设计和工艺实践。     

On the generation of test patterns for multiple faults

This article presents a new method to generate test patterns for multiple stuck-at faults in combinational circuits. We assume the presence of all multiple faults of all multiplicities and we do not resort to their explicit enumeration: the target fault is a single component of possibly several multiple faults. New line and gate models are introduced to handle multiple fault effect propagation through the circuits. The method tries to generate test conditions that propagate the effect of the target fault to primary outputs. When these conditions are fulfilled, the input vector is a test for the target fault and it is guaranteed that all multiple faults of all multiplicities containing the target fault as component are also detected. The method uses similar techniques to those in FAN and SOCRATES algorithms to guide the search part of the algorithm, and includes several new heuristics to enhance the performance and fault detection capability. Experiments performed on the ISCAS'85 benchmark circuits show that test sets for multiple faults can be generated with high fault coverage and a reasonable increase in cost over test generation for single stuck-at faults.     

Algorithms for I DDQ measurement based diagnosis of bridging faults

In the absence of information about the layout one is left with no alternative but to consider all bridging faults. An algorithm for diagnosis of a subset of such faults, viz. single two line bridging faults in static CMOS combinational circuits is presented. This algorithm uses results from I _DDQ measurement based testing.Unlike known diagnosis algorithms, this algorithm does not use fault dictionaries, it uses only logic simulation and uses no fault simulation. It also uses SOPS, a novel representation of subsets of two-line bridging faults resulting in an efficient algorithm.In spite of the large number of faults that we consider, our experimental results point to the computational feasibility of I _DDQ Measurement based diagnosis of single two line bridging faults. It also shows the effectiveness of reducing the set of possible faults using I _DDQ measurements.A preliminary version of this work was presented at the 29th ACM/IEEE Design Automation Conference, 1992.Research Partially Supported by NSF Grant No. MIP-9102509.This work was performed when the author was with the Dept. of Computer Science, State University of New York at Buffalo.     

A neural network algorithm for testing stuck-open faults in CMOS combinational circuits

In this article, an automatic test pattern generation technique using neural network models for stuck-open faults in CMOS combinational circuits is presented. For a gate level fault model of stuck-open faults in CMOS circuits, SR(slow-rise) and SF(slow-fall) gate transition faults we develop a neural network representation. A neural network computation technique for generating robust test patterns for stuck-open faults is given. The main result is extending previous efforts in stuck-at test pattern generation to stuck-open test pattern generation using neural network models. A second result is an extension of the technique to robust test pattern generation.     

CMOS集成电路静态功耗电流测试的重要性研究

目前,国内生产厂和用户针对CMOS集成电路静态电流的测试,仍基于现有的标准和产品规范。但是,采用这些测试方法来测试合格的器件,在使用过程中却发现了某些电路静态电流超差的现象。通过比较目前国内外的标准和规范所规定的方法,分析其存在的问题,并说明了静态电流测试的重要性。通过实验进行了验证说明,并提出了解决问题的建议。     

Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests

The ever increasing trend to reduce DPM levels of memories requires tests with very high fault coverage and low cost. This paper describes an important fault class, called dynamic faults, that cannot be ignored anymore. The dynamic fault behavior can take place in the absence of the static fault behavior, for which the conventional memory tests have been constructed. The concept of dynamic fault will be established and validated for both dynamic and static Random-Access-Memories. A systematic way to develop fault models for dynamic faults will be introduced. Further, it will be shown that conventional memory tests do not necessarily detect its dynamic faulty behavior, which has been shown to exist in real designs. The paper therefore also presents new memory tests to target the dynamic fault class.     

Algorithms to select I DDQ measurement points to detect bridging faults

I _DDQ measurement is a time consuming process. Thus, reducing the number of I _DDQ measurements have a great impact on the test time. Carefully selecting a few I _DDQ measurement points is therefore an important problem. This problem has been studied for detecting leakage faults but not for bridging faults. We present novel algorithms to select I _DDQ measurement points to detect bridging faults. Experimental results obtained are very encouraging. The method can also be used: by test generators to compress I _DDQ test sets; and to maximize the fault coverage when a fixed number of measurement points are given.Research supported by NSF Grant No. MIP-9102509.     

Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs

In this paper, a transparent test technique for testing permanent faults developed during field operation of DRAMs has been proposed. A three pronged approach has been taken in this work. First, a word oriented transparent March test generation algorithm has been proposed that avoids signature based prediction phase; next the proposed transparent March test is structured in a way that facilitates its implementation during refresh cycles of the DRAM; finally the on-chip refresh circuit is modified to allow its re-use during implementation of the proposed transparent March test on DRAM. Re-use of refresh cycles for test purpose ensures periodic testing of DRAM without interruption. Thus, faults are not allowed to accumulate. Moreover, wait for idle cycles of the processor to perform the test are avoided and test finishes within a definite time. Re-using the refresh circuit for test purpose overcomes requirement of additional Design-For-Testability hardware and brings down the area overhead.Both analytic predictions and simulation results for the method proposed here indicate real estate benefits and test time savings in comparison to other reported techniques. The proposed refresh re-use based transparent test technique provides a cost effective solution by providing facility for periodic tests of DRAM without requiring additional test hardware.     

FAULT DETECTION TEST SET FOR TESTABLE REALIZATIONS OF LOGIC FUNCTIONS WITH ESOP EXPRESSIONS

The circuit testable realization and its fault detection for logic functions with ESOP （EXOR-Sum-Of-Products） expressions are studied. First of all, for the testable realization by using XOR gate cascade, a test set with 2n ＋ m ＋ 1 vectors for the detections of AND bridging faults and a test set with 2n ＋ m vectors for the detections of OR bridging faults are presented. Secondly, for the testable realization by using ）（OR gate tree, a test set with 2n ＋ m vectors for the detections of AND bridging faults and a test set with 3n ＋ m ＋ 1 vectors for the detections of OR bridging faults are presented. Finally, a single fault test set with n ＋ 5 vectors for the XOR gate tree realization is presented. Where n is the number of input variables and m is the number of product terms in a logic function.     

Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits

We present a technique to statistically estimate path-delay fault coverage for synchronous sequential circuits. We perform fault-free simulation using a multivalue algebra and accumulate signal transition statistics, from which we calculate controllabilities of all signals and sensitization probabilities for all gates and flip-flops. We use a rated clock testing model where all time frames operate at the rated clock. We obtain path observabilities either by enumerating paths in the all-paths method, or by a nonenumerative method considering only the longest paths. The path-delay fault detectability is the product of observabilities of signals on paths from primary inputs (PIs) or pseudo-primary inputs (PPIs) to primary outputs (POs) or pseudo-primary outputs (PPOs), and the controllability on the corresponding PI or PPI. We use the optimistic update rule of Bose et al. for updating latches during logic simulation. When compared with exact fault simulation, the average absolute deviation in our statistical fault coverage estimation technique is 1.23% and the very worst absolute deviation was 6.59%. On average, our method accelerates delay fault coverage computation four times over an exact path delay fault simulator.     

Efficient March Tests for a Reduced 3-Coupling and 4-Coupling Faults in Random-Access Memories

This paper presents two new march test algorithms, MT-R3CF and MT-R4CF, for detecting reduced 3-coupling and 4-coupling faults, respectively, in n × 1 random-access memories (RAMs). To reduce the length of the tests, only the coupling faults between physically adjacent memory cells have been considered. The tests assume that the storage cells are arranged in a rectangular grid and that the mapping from logical addresses to physical cell locations is known completely. The march tests need 30n and 41n operations, respectively. In this paper any memory fault is modelled by a set of primitive memory faults called simple faults. We prove, using an Eulerian graph model, the ability of the test algorithms to detect all simple coupling faults. This paper also includes a study regarding the ability of the test MT-R3CF to detect interacting linked 3-coupling faults. This work improves the results presented in [1] where a similar model of reduced 3-coupling faults has been considered and a march test with 38n operations has been proposed. To compare these new march tests with other published tests, simulation results are presented in this paper.     

Crosstalk effects in mixed-signal ICs in deep submicron digital CMOS technology

This paper illustrates the crosstalk phenomenon and its impact on the design of mixed analog/digital circuits with high accuracy specifications. Generation of digital disturbs, propagation through the substrate, and effects on analog devices are considered, with particular emphasis on integrated circuits realized on heavily doped substrate, where traditional shielding is less effective. Techniques to reduce analog/digital crosstalk are reviewed and discussed. A simple modeling approach is presented, suitable for the analysis of crosstalk effects using a conventional electrical simulator (SPICE). Experimental results on a test chip are presented to validate the modeling approach.     

The effects of transistor source-to-gate bridging faults in complexCMOS gates

A study of the effect of gate-to-source bridging faults in the pull-up section of a complex CMOS gate is presented. The manifestation of these faults depends on the resistance value of the connection causing the bridging. It is shown that such faults manifest themselves either as stuck-at or stuck-open faults and can be detected by tests for stuck-at and stuck-open faults generated for the equivalent logic current. It is observed that for transistor channel lengths larger than 1 μm there exists a range of values of the bridging resistance for which the fault behaves as a pseudo-stuck-open fault     

Behavior Analysis of Internal Feedback Bridging Faults in CMOS Circuits

In this paper we analyze fault behaviors of internal feedback bridging faults. To investigate their behaviors, we use a simple circuit model consisting of 2-input NAND gate and NOT gate. From analysis results, we find that behaviors of internal feedback bridging faults are more complex than those of external feedback bridging faults. We expose that they cause IDDQ-only failure, internal latch and internal oscillation as well as latch and oscillation behavior. These phenomena are caused by the following facts: formation of an electrically conducting feedback loop and connection of the feedback loop with the circuit output depend on input values of the circuit, and the feedback loop is often alive only within the circuit. We also discuss methods for detecting this kind of fault.     

Simulating Single Event Transients in VDSM ICs for Ground Level Radiation

This work considers a SET (single event transient) fault simulation technique to evaluate the probability that a transient pulse, born in the combinational logic, may be latched in a storage cell. Fault injection procedures and a fast fault simulation algorithm for transient faults were implemented around an event driven simulator. A statistical analysis was implemented to organize data sampled from simulations. The benchmarks show that the proposed algorithm is capable of injecting and simulating a large number of transient faults in complex designs. Also specific optimizations have been carried out, thus greatly reducing the simulation time compared to a sequential fault simulation approach.     

Multiple fault detection in two-level multi-output circuits

It is often stated that in irredundant two-level logic circuits, a test set for all single stuck faults will also detect all multiple stuck faults. We show by a simple example that this result does not hold for multi-output circuits even when each output function is prime and irredundant. Using a result from the programmable logic array technology, we give an output ordering constraint that, if satisfied during test generation, will make a single stuck fault test set a valid multiple stuck fault test set for irredundant two-level multi-output circuits.