自旋场效应晶体管中隧道磁阻的势垒相关反转效应

考虑自旋场效应晶体管中Rashba自旋轨道相互作用和自旋输运量子相干性,研究了势垒强度对自旋场效应晶体管的自旋相关量子输运的影响. 研究发现,势垒强度较低时,隧道结电导随Rashba自旋轨道相互作用强度的变化呈现明显的振荡现象,势垒强度较高时,电导表现出明显的势垒相关“电导开关”现象. 当势垒强度逐渐增强时,平行结构电导呈现出单调下降趋势,而反平行结构电导产生波动,这种波动导致该隧道磁阻也随势垒强度的变化表现出振荡现象,且在合适的准一维电子气厚度情况下隧道磁阻值可以产生正负反转,这个效应将会在基于自旋的电子器件信息的存储上获得应用. 关键词： 自旋场效应管 开关效应 量子相干 隧道磁阻     

单根砷掺杂氧化锌纳米线场效应晶体管的电学及光学特性

采用化学气相沉积（CVD）的方法在砷化镓基底上合成直径为20 nm左右、长约数十微米的氧化锌纳米线,然后采用热扩散的方法,将生长于砷化镓基底之上的氧化锌纳米线通过600 ℃,30 min的有氧退火处理后,获得了砷掺杂的氧化锌纳米线.将获得的掺杂后的氧化锌纳米线采用电子束曝光以及真空溅射镀膜的方法将钛/金合金作为接触电极引出,从而构建成场效应晶体管.文中研究了单根氧化锌纳米线砷掺杂前后的电学特性,证实了通过砷掺杂来获得p型的氧化锌纳米线的可行性.构建的p型砷掺杂氧化锌场效应晶体管的跨导为35 nA/V,载流 关键词： p型ZnO纳米线 砷掺杂 场效应晶体管 光致发光     

Tin – an unlikely ally for silicon field effect transistors?

We explore the effectiveness of tin (Sn), by alloying it with silicon, to use SiSn as a channel material to extend the performance of silicon based complementary metal oxide semiconductors. Our density functional theory based simulation shows that incorporation of tin reduces the band gap of Si(Sn). We fabricated our device with SiSn channel material using a low cost and scalable thermal diffusion process of tin into silicon. Our high‐κ/metal gate based multi‐gate‐field‐effect‐transistors using SiSn as channel material show performance enhancement, which is in accordance with the theoretical analysis. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)     

Application of real space Kerker method in simulating gate-all-around nanowire transistors with realistic discrete dopants

We adopt a self-consistent real space Kerker method to prevent the divergence from charge sloshing in the simulating transistors with realistic discrete dopants in the source and drain regions. The method achieves efficient convergence by avoiding unrealistic long range charge sloshing but keeping effects from short range charge sloshing. Numerical results show that discrete dopants in the source and drain regions could have a bigger influence on the electrical variability than the usual continuous doping without considering charge sloshing. Few discrete dopants and the narrow geometry create a situation with short range Coulomb screening and oscillations of charge density in real space. The dopants induced quasilocalized defect modes in the source region experience short range oscillations in order to reach the drain end of the device.The charging of the defect modes and the oscillations of the charge density are identified by the simulation of the electron density.     

一种基于双栅材料的单极性类金属氧化物半导体碳纳米管场效应管设计方法

由于导电沟道-源/漏电极界面处可能发生的载流子带间隧穿,传统类金属氧化物半导体(MOS)碳纳米管场效应管呈现双极性传输特性,极大影响了器件性能的提高及其在电路中的应用.为获得具有理想单极性传输特性的类MOS碳纳米管场效应管,本文提出了一种基于双栅材料的器件设计方法.模拟结果表明,通过合理选取调节电极材料,在不影响器件亚阈值斜率的同时,该设计方法不仅能使开关电流比增大6—9个数量级,有效调节阈值范围,而且能有效消除传统类MOS碳纳米管场效应管的双极性传输特性.进一步研究表明,该设计所获得的器件性能提高与调节     

Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors

In this work, the effects of underlapping drain junction on the performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) have been studied in terms of direct-current (DC) characteristics including on-current (I_on), off-current (I_off), subthreshold swing (S), and I_on/I_off ratio. In addition, the dependences of intrinsic delay time (τ) and radio-frequency (RF) performances including cut-off frequency (f_T) and maximum oscillation frequency (f_max) on gate–drain capacitance (C_gd) with the underlapping were investigated as the gate length (L_gate) is scaled. A GAA TFET with asymmetric junctions, with an underlap at the drain side, demonstrated DC and RF performances superior to those of a device with symmetric junctions.     

Electronic transport properties of silicon junctionless nanowire transistors fabricated by femtosecond laser direct writing

Silicon junctionless nanowire transistor(JNT) is fabricated by femtosecond laser direct writing on a heavily n-doped SOI substrate.The performances of the transistor,i.e.,current drive,threshold voltage,subthreshold swing(SS),and electron mobility are evaluated.The device shows good gate control ability and low-temperature instability in a temperature range from 10 K to 300 K.The drain currents increasing by steps with the gate voltage are clearly observed from 10 K to50 K,which is attributed to the electron transport through one-dimensional(1D) subbands formed in the nanowire.Besides,the device exhibits a better low-field electron mobility of 290 cm~2·V~(-1)·s~(-1),implying that the silicon nanowires fabricated by femtosecond laser have good electrical properties.This approach provides a potential application for nanoscale device patterning.     

Ballistic transport in extended Datta-Das spin field effect transistors

The model of the Datta-Das spin field effect transistor [S. Datta, B. Das, Appl. Phys. Lett. 56 (1990) 665] is extended in several respects: (1) the Rashba effect and Dresselhaus effect coexist; (2) the incoming and outgoing leads are both ferromagnetic; (3) the interfacial scattering and band mismatch are taken into account. By using the Griffith boundary conditions, the transmission coefficients and, thus, the Landauer-Büttiker conductance are obtained analytically. The transmission probability and conductance of the spin field effect transistor are studied in detail.     

Electric-field-dependent charge delocalization from dopant atoms in silicon junctionless nanowire transistor

We study electric-field-dependent charge delocalization from dopant atoms in a silicon junctionless nanowire transistor by low-temperature electron transport measurement. The Arrhenius plot of the temperature-dependent conductance demonstrates the transport behaviors of variable-range hopping(below 30 K) and nearest-neighbor hopping(above 30 K).The activation energy for the charge delocalization gradually decreases due to the confinement potential of the conduction channel decreasing from the threshold voltage to the flatband voltage. With the increase of the source–drain bias, the activation energy increases in a temperature range from 30 K to 100 K at a fixed gate voltage, but decreases above the temperature of 100 K.     

描述光伏效应的新解析模型

对陆启生等人提出的描述光伏效应的解析模型涉及的边界条件进行了讨论,提出了一个适用性更宽的解析模型。通过对新模型、陆的模型以及另一个解析模型的比较,对前两个模型能够描述光伏型光电探测器在强光辐照时的信号饱和效应的原因进行了解释。     

双栅调控的硅量子线中的库仑振荡效应

基于单电子隧穿和库仑阻塞效应,研究了硅量子线中的单电子输运特性.利用绝缘体上硅薄膜材料作为衬底构建侧栅结构的硅量子线单电子晶体管,通过背栅和侧栅对量子线的电子输运特性进行调制.实验发现,在硅量子线中分别观察到背栅和侧栅调制的单电子效应和库仑振荡现象.从微分电导的二维灰度轮廓图,清楚地观察到了库仑阻塞区,说明由于栅压导致在硅量子线中形成了库仑岛. 关键词： 库仑振荡 单电子效应 硅量子线     

Ballistic transport in nanoscale field effect transistors revealed by four-terminal DC characterization

We show that four-terminal measurements of the differential conductance of field effect transistors (FETs) can provide important insights into the transport mechanism, and in particular can reveal the presence of ballistic transport. Measurements and simulations of purposely fabricated AlGaAs–GaAs heterostructure FETs show that ballistic transport results in a pronounced peak in the derivative of the differential conductance versus the gate voltage, which splits into two peaks with increasing drain-to-source voltage. Analyzing the four-probe conductance, ballistic electron transport through the channel is revealed as the origin of the observed peak splitting.     

Analytical model of the drain current in amorphous silicon junction field effect transistors

This paper presents an analytical model of a hydrogenated amorphous silicon (a-Si:H) junction field effect transistor (JFET) based on a p-type/intrinsic/n-type stacked structure. The p-doped layer is connected to the transistor gate electrode, while the n-layer acts as the device channel. The analysis shows the effect of the geometrical and physical parameters of the intrinsic and n-doped layers on the transistor characteristics. In particular, the intrinsic layer thickness plays a central role in determining the depletion region of the n-channel and, as a consequence, the device threshold voltage. The drain current behavior achieved with a modeled parametric analysis is in very good agreement with the experimental drain current measured on fabricated JFET, both in triode and pinch-off regions. This demonstrates the model feasibility as an effective tool to design thin film electronic circuit as a sensor signal amplifier based on a-Si:H p-i-n junction.     

隧道场效应晶体管静电放电冲击特性研究

随着器件尺寸的不断减小,集成度的逐步提高,功耗成为了制约集成电路产业界发展的主要问题之一.由于通过引入带带隧穿机理可以实现更小的亚阈值斜率,隧道场效应晶体管(TFET)器件已成为下一代集成电路的最具竞争力的备选器件之一.但是TFET器件更薄的栅氧化层、更短的沟道长度容易使器件局部产生高的电流密度、电场密度和热量,使得其更容易遭受静电放电(ESD)冲击损伤.此外,TFET器件基于带带隧穿机理的全新工作原理也使得其ESD保护设计面临更多挑战.本文采用传输线脉冲的ESD测试方法深入分析了基本TFET器件在ESD冲击下器件开启、维持、泄放和击穿等过程的电流特性和工作机理.在此基础之上,给出了一种改进型TFET抗ESD冲击器件,通过在源端增加N型高掺杂区,有效的调节接触势垒形状,降低隧穿结的宽度,从而获得更好的ESD设计窗口.     

双势垒磁性隧道结的磁电阻效应及其在自旋晶体管中的应用

利用磁控溅射方法沉积双势垒磁性隧道结多层膜, 其中Al-O势垒层由等离子体氧化1 nm厚的 金属铝膜方式制备，然后采用深紫外光曝光和Ar离子刻蚀技术、微加工制备出长短轴分别为 6和3 μm大小的椭圆形双势垒磁性隧道结（DBMTJ），并在室温和低温下对其自旋电子输运 特性进行了研究. DBMTJ的隧穿磁电阻(TMR)比值在室温和42 K分别达到27％和423％， 结电阻分别为136 kΩ·μm²和175 kΩ·μm²，并在实验中观 察到平行状 态下存在低电阻态及共振隧穿效应，反平行态下呈现高电阻态以及TMR随外加偏压或直流电 流的增加而发生振荡现象. 由此，设计了一种基于这种双势垒磁性隧道结隧穿特性的自旋晶 体管. 关键词： 双势垒磁性隧道结 隧穿磁电阻 共振隧穿效应 自旋晶体管     

Electron energy loss spectroscopy of ultrathin pentacene field effect transistors

Electron energy loss spectra of ultrathin pentacene field effect transistors were measured by applying gate bias voltages. Tailing and shouldering of the primary peak on the energy loss side was observed for 1.5 nm thick films when a negative gate bias was applied. The energy loss spectra obtained from the deconvolution of the primary electron profile showed peaks, and the peak energies increased as a function of the gate bias voltage. This is consistent with the behavior of two-dimensional plasmons of field-induced carriers. The thickness dependence is explained by the thickness of the accumulation layer and the probing depth of the spectroscopy.     

描述光伏效应的新解析模型

 对陆启生等人提出的描述光伏效应的解析模型涉及的边界条件进行了讨论，提出了一个适用性更宽的解析模型。通过对新模型、陆的模型以及另一个解析模型的比较，对前两个模型能够描述光伏型光电探测器在强光辐照时的信号饱和效应的原因进行了解释。     

Modeling of the drain-induced barrier lowering effect and optimization for a dual-channel 4H silicon carbide metal semiconductor field effect transistor

A new analytical model to describe the drain-induced barrier lowering (DIBL) effect has been obtained by solving the two-dimensional (2D) Poisson's equation for the dual-channel 4H-SiC MESFET (DCFET). Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.     

Design optimization of tunneling field-effect transistor based on silicon nanowire PNPN structure and its radio frequency characteristics

Recently, a number of semiconductor devices have been widely researched in order to make breakthroughs from the short-channel effects (SCEs) and high standby power dissipation of the conventional metal-oxide-semiconductor field-effect transistors (MOSFETs). In this paper, a design optimization for the silicon nanowire tunneling field-effect transistor (SNW TFET) based on PNPN multi-junction structure and its radio frequency (RF) performances are presented by using technology computer-aided design (TCAD) simulations. The design optimization was carried out in terms of primary direct-current (DC) parameters such as on-current (I_on), off-current (I_off), current ratio (I_on/I_off), and subthreshold swing (SS). Based on the parameters from optimized DC characteristics, basic radio frequency (RF) performances such as cut-off frequency (f_T) and maximum oscillation frequency (f_max) were analyzed. The simulated device had a channel length of 60 nm and a SNW radius of 10 nm. The design variable was width of the n-doped layer. For an optimally designed PNPN SNW TFET, SS of 34 mV/dec and I_on of 35 μA/μm were obtained. For this device, f_T and f_max were 80 GHz and 800 GHz, respectively.     

Simulations of monolayer SiC transistors with metallic 1T-phase MoS2 contact for high performance application

We preform a first-principles study of performance of 5 nm double-gated (DG) Schottky-barrier field effect transistors (SBFETs) based on two-dimensional SiC with monolayer or bilayer metallic 1T-phase MoS₂ contacts. Because of the wide bandgap of SiC, the corresponding DG SBFETs can weaken the short channel effect. The calculated transfer characteristics also meet the standard of the high performance transistor summarized by international technology road-map for semiconductors. Moreover, the bilayer metallic 1T-phase MoS₂ contacts in three stacking structures all can further raise the ON-state currents of DG SiC SBFETs in varying degrees. The above results are helpful and instructive for design of short channel transistors in the future.