字符型嵌入式软PLC虚拟机设计

介绍一种可直接解析字符型语句表指令的字符型嵌入式软PLC虚拟机。该虚拟机主要运行于嵌入式操作系统上,可直接对字符型语句表指令进行解析和处理,而无需对语句表进行编译即可下载到嵌入式软PLC系统中运行。     

基于ARM的编译型可编程序控制器系统研究

可编程序控制器是电气自动化控制领域的重要组成部分,其性能的优劣对整个控制系统有着重大的影响.针对用户程序比较复杂时,采用编程指令的解释执行方式的PLC系统执行效率低、可移植性差等不足,提出一种基于ARM的编译型PLC系统构建方法,理论分析和测试实验都表明了这种方法的可靠性和高效性.     

电磁兼容用PLC汽车驾驶器电控单元的设计

为了在电磁兼容测试时远程控制汽车的驾驶状态,研制了一套自动化汽车驾驶系统.驾驶系统中的电控单元基于PLC进行设计,并使用Step7对电控单元进行硬件组态和程序设计.PLC程序的核心功能是如何接收来自PC的指令,并转换成符合要求的控制电压信号,以此控制气动执行机构动作.介绍了VB.net环境下的上位机程序的设计与编译.PLC电控单元通过接收上位机的指令对气动控制器发送控制信号,从而实现对汽车驾驶状态的控制.系统完成后可手动或自动控制汽车的行驶状态,运行效果良好.     

基于ARM-FPGA的PLC源程序编译系统的设计

在研究PLC程序编译执行过程和新指令特点的基础上,基于ARM-FPGA的PLC主机结构,提出一种新型PLC指令的编译方法。静态编译将指令的操作数转换为PLC软元件的直接地址,建立转移类指令的转移地址链表,编译成为新的PLC程序代码序列;动态编译在PLC程序执行过程中将新程序指令中操作数的直接地址转换为立即数,由FPGA模块执行。通过对PLC用户源程序的编译与执行,表明该方法能够充分应用FPGA高速并行处理的功能,提高了PLC程序执行的速度。     

PLC源程序编码方法与解释执行算法设计

传统PLC源程序的编译方法,虽然执行速度快,占用资源少,但可移植性差不够灵活;传统PLC源程序的解释方法虽然灵活性好,但执行速度慢且占用存储空间大。为了兼顾存储空间、执行速度和可移植性,给出了一种PLC源程序的编码方法,减少了存储空间,简化了解释执行算法,并在表达式求值算法和传统PLC解释执行算法的基础之上,充分利用逻辑运算的性质,提出了改进的PLC解释执行算法,大大减少了逻辑运算的步数,提高了PLC系统运行的速度。     

编译执行在可编程逻辑控制器上的实现

传统的可编程逻辑控制器(PLC)采用解释执行方式执行梯形图,执行效率低下.对此该文提出以编译执行方式代替解释执行方式来提高执行效率.但通常的编译执行方式实现难度巨大,因此本文提出利用GNU编译器集(GCC)实现编译执行的解决方法.即先将梯形图转换为C语言程序,然后通过GCC的开放平台得到编译执行所需的各工具,并运用这些工具编译C语言程序从而实现PLC的编译执行方式.测试表明编译执行的PLC执行效率大幅提升.     

111机的某机解释系统(JS)介绍

111机的某机解释系统(以下记称为 JS),是用于在111机上解释执行某机的机器指令,提供在111机上调试某机机器指令程序(记作 PM)的手段。一、功能JS 具有如下功能。1.指令部分1)对某机的运算型指令,均各按其操作功能予以解释执行。2)对某机的控制型指令。1°.600～630、634～636、670～756、772等操作,按其操作功能予以解释执行。     

水电站机组监控系统中上位机与下位机的通信实现

介绍了在水电站机组监控系统中,如何利用VB来实现上位机与三菱FX系列PLC的通信,上位机与三菱FX系列PLC之间采用计算机链接通信方式.并介绍了水电站机组监控系统的通信方式、通信规约以及所采取的提高通信可靠性的措施.经水电站实际运行证明,该通信方式运行稳定、可靠.     

基于PLC 的供热网络远程监控系统研

研究PLC 网络及其通信方法,以建立一个网络化的远程监控系统。Omron 可编程控制器(PLC) 对各换热站和 给水泵房进行现场的实时监控;借助企业已存的电话网络作为上位监控计算机和下位PLC 之间的通信介质,根据 上位机链接命令的帧格式和Modem的AT指令,使用VB 编写通信程序;并且,利用PLC 网络的无协议通信方式进行 下位机的主动拨号报警。该系统实现了换热站和泵房的无人值守。     

基于嵌入式PC的工业机器人开放式控制系统交互控制的实现

为了满足多自由度关节型工业机器人多机交互控制的需求,以嵌入式工业PC为硬件平台,RT-Linux操作系统为软件平台,采用模块化的软件设计方法,设计了工业机器人开放式控制系统。该系统采用共享内存的方式实现内外部信号的交互,通过执行PLC程序中定义的不同的M指令来实现与外部系统的交互控制功能。在浇铸机器人交互控制中的实际应用表明:该控制系统开放性好,实时性强,运行稳定可靠。     

基于嵌入式软PLC分布式控制系统设计

为了确保PC端主机所生成指令程序满足PLC控制原则,使PLC编程器的逻辑编译能力得到保障,提高指令编码准确性,设计基于嵌入式软PLC分布式控制系统。根据软PLC定义标准,确定系统结构的组成形式,再通过分析工作执行机制的方式,完成对嵌入式软PLC系统的技术基础研究。在分布式体系中,同时开发I/O驱动程序与PLC执行程序,并联合下级PLC编程器设备,确定CODESYS工程组件的实时运行状态,完成分布式控制系统的I/O组件设计。按照实时内核的进入与退出模式,定义分时映像区取值范围,借助数据库主机中存储的控制指令执行程序,求解指令逻辑栈表达式,实现对软PLC驱动模式的规范,完成基于嵌入式软PLC分布式控制系统设计。实验结果表明,本次实验所选10条指令程序的PC端输出结果均满足PLC控制原则,在保障PLC编程器逻辑编译能力方面具有突出作用价值,且能够有效提高指令编码准确性。     

基于嵌入式机器码的软件PLC系统研究

针对基于虚拟机机制的软件PLC可移植性差,执行效率低等不足,研究基于嵌入式机器码的软件PLC系统,通过梯形图编译器、代码解析生成器、汇编编译器等处理,将用户开发的逻辑程序直接编译成能够在CPU环境下执行的嵌入式机器码,该方法减少PLC虚拟指令执行过程,提高软件PLc执行效率.     

Reducing the overhead of dynamic compilation

The execution model for mobile, dynamically‐linked, object‐oriented programs has evolved from fast interpretation to a mix of interpreted and dynamically compiled execution. The primary motivation for dynamic compilation is that compiled code executes significantly faster than interpreted code. However, dynamic compilation, which is performed while the application is running, introduces execution delay. In this paper we present two dynamic compilation techniques that enable high performance execution while reducing the effect of this compilation overhead. These techniques can be classified as (1) decreasing the amount of compilation performed, and (2) overlapping compilation with execution. We first present and evaluate lazy compilation, an approach used in most dynamic compilation systems in which individual methods are compiled on‐demand upon their first invocation. This is in contrast to eager compilation, in which all methods in a class are compiled when a new class is loaded. In this work, we describe our experience with eager compilation, as well as the implementation and transition to lazy compilation. We empirically detail the effectiveness of this decision. Our experimental results using the SpecJVM Java benchmarks and the Jalapeño JVM show that, compared to eager compilation, lazy compilation results in 57% fewer methods being compiled and reductions in total time of 14 to 26%. Total time in this context is compilation plus execution time. Next, we present profile‐driven, background compilation, a technique that augments lazy compilation by using idle cycles in multiprocessor systems to overlap compilation with application execution. With this approach, compilation occurs on a thread separate from that of application threads so as to reduce intermittent, and possibly substantial, delay in execution. Profile information is used to prioritize methods as candidates for background compilation. Methods are compiled according to this priority scheme so that performance‐critical methods are invoked using optimized code as soon as possible. Our results indicate that background compilation can achieve the performance of off‐line compiled applications and masks almost all compilation overhead. We show significant reductions in total time of 14 to 71% over lazy compilation. Copyright © 2001 John Wiley & Sons, Ltd.     

基于ARM+FPGA的嵌入式安全PLC设计

传统的PLC系统由于自身系统结构和处理器性能等问题,在执行工业控制的过程中往往在执行了一定时间后系统就会发生惯性停机,影响工业生产.提出了基于ARM+FPGA高性能双处理器的嵌入式安全PLC结构模型,可以大幅降低系统失效的概率,提高工业控制可靠性.本系统分为硬件结构和软件系统两大部分.硬件部分采用了1oo2D双通道异构冗余安全体系结构,两条通道配备有安全电路,两个处理器之间设计有安全诊断电路,通过交叉检测判断系统运行是否正常.软件部分主要包括编译系统和执行系统,编译系统将编写的PLC程序转换成机器可执行的代码也叫做目标代码,再由执行系统进行目标代码的执行.     

A MATLAB subset to C compiler targeting embedded systems

This paper describes MATISSE, a compiler able to translate a MATLAB subset to C targeting embedded systems. MATISSE uses LARA, an aspect‐oriented programming language, to specify additional information and transformations to the input MATLAB code, for example, insertion of code for initialization of variables, and specification of types and shapes of variables. The compiler is being developed bearing in mind flexibility, multitarget and multitoolchain support, allowing for the generation of several implementations in C from the same reference code in MATLAB. In this paper, we also present a number of techniques being employed in MATLAB to C compilation, such as element‐wise mapping operations, matrix views, weak types, and intrinsics. We validate these techniques using MATISSE and a set of representative benchmarks. More specifically, we evaluate the compiler with a set of 31 benchmarks using an embedded system board and a desktop computer. The results show speedups up to 1.8× by employing information provided by LARA aspects, when compared with C code generated without additional user information. When compared with the execution time of the original code running on MATLAB, the execution time of the generated C code achieved a geometric mean speedup of 13×. Copyright © 2016 John Wiley & Sons, Ltd.     

一个基于混合并发模型的Java虚拟机

从解释执行到及时编译的转变极大地提高了Java程序的运行速度.但是,现有的Java虚拟机还有待进一步的改进.提出了一种新的Java虚拟机编译与执行模型--混合并发模型HCCEM(hybrid concurrent compilation and execution model).该模型通过多线程控制方式将字节码的编译与执行过程相重叠,从而获取加速的效果.另外还给出了基于HCCEM的Java虚拟机JAFFE的设计方案,并就实现中的执行模式切换、异常处理以及层次线程等问题进行了讨论.实验结果表明,HCCEM能     

基于电话网实现上位机与三菱PLC的远程通信

研究了基于电话网实现了上位机与FX2N系列PLC远距离通信的方法。罗列了该系列PLC的通信模式，详细介绍了该系列PLC编程器的通信协议。具体阐述了在Visual C＋＋环境下，用MSComm控件实现串口通信的方法，并给出了串口初始化代码、Modem拨号及程序代码、数据帧生成及发送的程序代码等的实现程序。为进一步实现上位机对PLC的远距离监控提供了参考。     

Efficiently Adapting Java Binaries in Limited Memory Contexts

This paper presents a compilation framework that allows executable code to be shared across different Java Virtual Machine (JVM) instances. Current compliant JVMs for servers are burdened with large memory footprints (because of the size of the increasingly complicated compilers) and high startup costs, while compliant JVMs for embedded devices typically rely on interpretation. This paper describes a quasi-static approach that allows execution of a read-only version of the code, enabling compiled Java binaries to be embedded in ROM in an embedded environment or shared across multiple applications in a server environment. We have implemented this approach in the Quicksilver quasi-static compiler for the Jikes RVM (Jikes Research Virtual Machine). On the SPECjvm98 benchmark suite, our approach gives writable memory space savings of between 82–89% over that of our previous (non-sharable, non-ROMable) quasi-static approach, while delivering performance that is typically within 1–7% of that approach, and is competitive with the performance of the Jikes RVM adaptive optimization system.     

Improving on Linear Scan Register Allocation

Register allocation is a major step for all compilers. Various register allocation algorithms have been developed over the decades. This work describes a new class of rapid register allocation algorithms and presents experimental data on their behavior. Our research encourages the avoidance of graphing and graph-coloring based on the fact that precise graph-coloring is nondeterministic polynomial time-complete (NP-complete), which is not suitable for real-time tasks. In addition, practical graph-coloring algorithms tend to use polynomial-time heuristics. In dynamic compilation environments, their super linear complexity makes them unsuitable for register allocation and code generation. Existing tools for code generation and register allocation do not completely fulfill the require- ments of fast compilation. Existing approaches either do not allow for the optimization of register allocation to be achieved compre- hensively with a sufficient degree of performance or they require an unjustifiable amount of time and/or resources. Therefore, we pro- pose a new class of register allocation and code generation algorithms that can be performed in linear time. These algorithms are based on the mathematical foundations of abstract interpretation and the computation of the level of abstraction. They have been implemen- ted in a specialized library for just-in-time compilation. The specialization of this library involves the execution of common intermedi- ate language (CIL) and low level virtual machine (LLVM) with a focus on embedded systems.