A 60 GHz receiver front-end with PLL based phase controlled LO generation for phased-arrays

This paper presents a front-end architecture for fully integrated 60 GHz phased array receivers. It employs LO-path beamforming using a phase controlled phase-locked loop (PC-PLL). To demonstrate the architecture a circuit is implemented featuring a two stage low noise amplifier, two cascaded active mixers, and a PC-PLL. The receiver downconverts the 60 GHz signal in two steps, using LO signals from the 20 GHz QVCO of the PLL. A differential 2nd-order harmonic is coupled from the sources of the current commutating pairs of the QVCO, feeding the LO-port of the first mixer and downconverting the 60 GHz RF signal to a 20 GHz intermediate frequency. Quadrature 20 GHz LO signals are then used in the second mixer to down-convert the IF signal to baseband. The PLL is locked to a relatively high reference frequency, 1.25 GHz, which reduces the size of the PLL loop filter and enables a compact layout. The measurements show an input return loss better than ?10 dB between 57.5 and 60.8 GHz, a 15 dB voltage gain, and a 9 dB noise figure. Two-tone measurements show ?12.5 dBm IIP3, 29 dBm IIP2, and ?24 dBm ICP1. The PC-PLL phase noise is ?105 dBc/Hz at 1 MHz offset from a 20 GHz carrier, and the phase of the received 60 GHz signal is digitally controllable with a resolution of 3.2°, covering the full 360° range with a phase error smaller than 1°. The chip consumes 80 mA from a 1.2 V supply, and measures 1,400 μm × 660 μm (900 μm × 500 μm excluding pads) including LNAs, mixers, and PC-PLL in a 90 nm RF CMOS process.     

A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur

This paper presents a 5.7–6.0 GHz Phase-Locked Loop (PLL) design using a 130 nm 2P6M CMOS process. We propose to suppress reference spur through reducing the current mismatch in charge pump (CP), controlling the delay time in phase frequency detector (PFD), and using a smaller VCO gain (KVCO). With a reference frequency of 32.768 MHz, chip measurement results show that the frequency tuning range is 5.7–6.0 GHz, the reference spur is −68 dBc, the phase noise levels are −109 dBc/Hz and −135 dBc/Hz at 1 MHz and 10 MHz offset respectively for 5.835 GHz. Compared with existing designs in the literature, this work’s reference spur is improved by at least 17% and its phase noise is the lowest. Under a 1.5 V supply voltage, the power dissipation with an output buffer of the PLL is 12 mW.     

A 0.3–3.5 GHz active-feedback low-noise amplifier with linearization design for wideband receivers

LNAs for wideband receivers usually require a high linearity to protect the desired signals from out-band interference. Active feedback LNAs always suffer from the nonlinear feedback of source follower, and present a poor linearity. In order to solve this problem, a complementary source follower (CSF) is proposed, which utilizes the different characteristic of NMOS and PMOS to linearize the source follower, leading to an improvement of LNA’s IIP₃ and IIP₂ by about 10 dBm and 21 dBm respectively. In addition, a post-distortion technique is also used on the common source stage, which further enhances the IIP₃ by about 2 dBm and IIP₂ by 11 dBm. After using the two techniques, the noise figure (NF) does not deteriorate; instead it achieves a 0.3 dB improvement. A prototype is designed in TSMC 0.18 μm CMOS process, and a 14.8 mW power is dissipated from a 1.6 V supply. In typical process corner, across 0.3 to 3.5 GHz, this LNA achieves a 14.6 dB gain, a 2.9 dB minimum NF, and an IIP₂ larger than +22 dBm and IIP₃ larger than +1.2 dBm.     

A low power 3-5 GHz CMOS UWB receiver front-end

A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 × 1.5 mm^2.     

A coin-battery-powered LDO-Free 2.4-GHz Bluetooth Low Energy/ZigBee receiver consuming 2 mA

This paper describes a 1.5-V low dropout regulator (LDO)-free ultra-low-power 2.4-GHz CMOS receiver for direct-powering through a coin battery. By effective merging the quadrature low noise amplifier (LNA), in phase and quadrature (I/Q) mixers, a voltage controlled oscillator (VCO) and a trans-impedance amplifier (TIA) in one cell, while removing the LDO, we fully utilize the available 1.5-V voltage supply for current-reuse between blocks, minimizing the dc current consumption. Specifically, a quadrature LNA operating as both common-source and common-drain provides the I/Q outputs in the signal path. Forward-body-bias applied to the transconductance stage of the I/Q mixers relaxes their voltage headroom consumption. Prototyped in 180-nm CMOS, the receiver exhibits a conversion gain (CG) of 23 dB, a noise figure (NF) of 13.8 dB and an input-referred 3rd-order intercept point (IIP3) of −14 dBm while consuming only 2 mA. The phase noise of the VCO is −118.5 dBc/Hz at 2.5 MHz offset. The low-cost technology and low current consumption renders the receiver suitable for Internet of Things (IoT) devices using the Bluetooth Low Energy (BLE) or ZigBee standards.     

A 0.1–1 GHz low power RF receiver front-end with noise cancellation technique for WSN applications

A low power 0.1–1 GHz RF receiver front-end composed of noise-cancelling trans-conductor stage and I/Q switch stage was presented in this paper. The RF receiver front-end chip was fabricated in 0.18 µm RF CMOS. Measurement results show the receiver front-end has a conversion gain of 28.1 dB at high gain mode, and the single-sideband (SSB) noise figure is 6.2 dB. In the low gain mode, the conversion gain of the receiver front-end is 15.5 dB and the IP1dB is −12 dBm. In this design, low power consumption and low cost is achieved by current-reuse and inductor-less topology. The receiver front-end consumes only 5.2 mW from a 1.8 V DC supply and the chip size of the core circuit is 0.12 mm².     

A novel 0.84 ppm/°C CMOS curvature-compensated bandgap with 1.2 V supply voltage

This paper proposes a novel CMOS curvature-compensated bandgap reference (BGR) by using a new full compensation technique. The theory behind the proposed full compensation technique is analyzed. The proposed BGR is designed and implemented using 0.15 μm standard CMOS process. Simulation results show that the proposed BGR achieves a temperature coefficient (TC) of 0.84 ppm/°C over the temperature range from −40 °C to 120 °C with a 1.2 V supply voltage. The current consumption of proposed BGR is 51 μA at 27 °C. The line regulation of proposed BGR is 0.023%/V over the supply voltage range from 1.2 V to 1.8 V at 27 °C. In addition, the PSRRs of proposed BGR are −91 dB, −81 dB, −61 dB and −29 dB at DC or 10 Hz, 1 kHz, 10 kHz, and 100 kHz, respectively.     

A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback

This paper presents a wireless receiver front-end intended for cellular applications implemented in a 65 nm CMOS technology. The circuit features a low noise amplifier (LNA), quadrature passive mixers, and a frequency divider generating 25 % duty cycle quadrature local oscillator (LO) signals. A complementary common-gate LNA is used, and to meet the stringent linearity requirements it employs positive feedback with transistors biased in the sub-threshold region, resulting in cancellation of the third order non-linearity. The mixers are also linearized, using a baseband to LO bootstrap circuit. Measurements of the front-end show about 3.5 dB improvement in out-of-band IIP3 at optimum bias of the positive feedback devices in the LNA, resulting in an out-of-band IIP3 of 10 dBm. With a frequency range from 0.7 to 3 GHz the receiver front-end covers most important cellular bands, with an input return loss above 9 dB and a voltage gain exceeding 16 dB for all bias settings. The circuit consumes 4.38 mA from a 1.5 V supply.     

A transformer-loaded receiver front end for 2.4 GHz WLAN in 0.13μm CMOS technology

A 2.4 GHz radio frequency receiver front end with an on-chip transformer compliant with IEEE 802.11b/g standards is presented.Based on zero-IF receiver architecture,the front end comprises a variable gain common-source low noise amplifier with an on-chip transformer as its load and a high linear quadrature folded Gilbert mixer.As the load of the LNA,the on-chip transformer is optimized for lowest resistive loss and highest power gain.The whole front end draws 21 mA from 1.2 V supply,and the measured results show a double side band noise figure of 3.75 dB,-31 dBm IIP3 with 44 dB conversion gain at maximum gain setting.Implemented in 0.13μm CMOS technology,it occupies a 0.612 mm~2 die size.     

A folded-cascode mixer for mixing-spur suppressions in a 2.4-to-5.8 GHz transmitter

This paper presents a folded-cascode mixer for an ISM band transmitter that translates the signals at the 2.4 GHz band to 5.8 GHz. Comparing to the conventional Gilbert cell mixer, our proposed folded-cascode mixer architecture with DC offset blocking, and transconductance linearization techniques can effectively suppress the LO feedthrough by 9 dB. The proposed mixer is designed in 0.11 μm CMOS and consumes 2.6 mA from a 1.2 V supply. The simulation results show that the mixer achieves an output power of 4.7 dBm, and all the emission spurs are well below −40dBc.     

A 0.1–4 GHz SDR receiver with reconfigurable 10–100 MHz signal bandwidth in 65 nm CMOS

A 0.1–4 GHz software-defined radio (SDR) receiver with reconfigurable 10–100 MHz signal bandwidth is presented. The complete system design methodology, taking blocker effects into account, is provided. Fully differential Op-Amp with Miller feedback and feed-forward compensations is proposed to support wideband analog circuits with low power consumption. The stability and isolation of inverter-based trans-conductance amplifier are analyzed in details. The design approach of high linearity Tow-Thomas trans-impedance amplifier is presented to reject out-of-band blockers. To compensate for PVT variations, IIP2, frequency tuning, DC offset and IQ calibration are also integrated on-chip. The SDR receiver has been implemented in 65 nm CMOS, with 1.2/2.5 V power supply and a core chip area of 2.4 mm². The receiver achieves S11 input matching below ?10 dB and a NF of 3–8 dB across the 0.1–4 GHz range, and a maximum gain of 82–92 dB with a 70 dB dynamic range. Dissipated power spans from 30 to 90 mW across this entire frequency range. For LTE application with 20 MHz signal bandwidth and a LO frequency of 2.3 GHz, the receiver consumes 21 mA current.     

A one-path subsampling quadrature receiver based on a ΣΔ modulator with distributed resonators

This article presents experimental results of a quadrature bandpass sigma–delta (ΣΔ) modulator based on distributed resonators. The modulator employs transmission lines and transconductors as main components and does not require switches in the loop filter as in the case of switched-capacitor (discrete-time) filters. In addition, the proposed complex modulator does not require a quadrature mixer in the receiver. As main feature, the modulator architecture introduces an innovative way to produce the I and Q outputs that is immune to path mismatch due to the sharing of all the analog circuitry for both paths. The one-bit second-order modulator ADC is able to convert IF signals at fs/2 and 3fs/2 (fs = 50 MHz), achieving an ENOB = 10 bits within a 1 MHz signal bandwidth. Therefore the modulator may be feasible for the typical IF frequencies used in cellular base stations. Furthermore, it provides an image rejection grater than 70 dB. The 0.35 μm BiCMOS chip consumes 28 mW at 3.3 V supply voltage.     

A landscape of β-Ga2O3 Schottky power diodes

β-Ga₂O₃ Schottky barrier diodes have undergone rapid progress in research and development for power electronic applications. This paper reviews state-of-the-art β-Ga₂O₃ rectifier technologies, including advanced diode architectures that have enabled lower reverse leakage current via the reduced-surface-field effect. Characteristic device properties including on-resistance, breakdown voltage, rectification ratio, dynamic switching, and nonideal effects are summarized for the different devices. Notable results on the high-temperature resilience of β-Ga₂O₃ Schottky diodes, together with the enabling thermal packaging solutions, are also presented.     

A self-duty-cycled 7.2–8.5 GHz IR-UWB receiver for low power and low data rate applications

A self-duty-cycled non-coherent impulse radio-ultra wideband receiver targeted at low-power and low-data-rate applications is presented. The receiver is implemented in a 130 nm CMOS technology and works in the 7.2–8.5 GHz UWB band, which covers the IEEE 802.15.4a and 802.15.6 mandatories high-band channels. The receiver architecture is based on a non-coherent RF front-end (high gain LNA and pulse detector) followed by a synchronizer block (clock and data recovery or CDR function and window generation block), which enables to shut down the power-hungry LNA between pulses to strongly reduce the receiver power consumption. The main functions of the receiver, i.e. the RF front-end and the CDR block, were measured stand-alone. A maximum gain of 40 dB at 7.2 GHz is measured for the LNA. The RF front-end achieves a very low turn-on time (<1 ns) and an average sensitivity of ?92 dBm for a 10^?3 BER at a 1 Mbps data rate. A root-mean-square (RMS) jitter of 7.9 ns is measured for the CDR for a power consumption of 54 µW. Simulation results of the fully integrated self-duty-cycled 7.2–8.5 GHz IR-UWB receiver (that includes the measured main functions) confirm the expected performances. The synchronizer block consumes only 125 µW and the power consumption of the whole receiver is 1.8 mW for a 3% power duty-cycle (on-window of 30 ns).     

A heterodyne interferometric polarimeter with 28μm H2O laser for Faraday rotation measurement

A fast response frequency-modulated interferometric polarimeter was designed and constructed with a single 28 μm H₂O laser for high density plasma diagnostics. This newly developed modulation system employs an electro-magnetically driven movable mirror to achieve the modulation frequency beyound 1 MHz for about 100 μs duration. The movable mirror performance is studied experimentally in detail. The determination of the Faraday rotation angle is based on the zero-crossing method for the observed beat signals produced by two kinds of rotating plane-polarized waves. The feasibility of the polarimeter constructed was verified in experiments of a field-reversed thetapinch plasma.     

A 220 GHz dynamic frequency divider in 0.5 μm InP DHBT technology

A high performance 3 inch 0.5 μ m InP DHBT technology with three interconnecting layers has been developed. The epitaxial layer structure and geometry parameters of the device were carefully studied to get the required performances. The 0.5×5 μm² InP DHBTs demonstrated f_t=350 GHz, f_max=532 GHz and BV_CEO=4.8 V, which were modeled using Agilent-HBT large signal model. As a benchmark circuit, a dynamic frequency divider operating from 110 to 220 GHz has been designed, fabricated and measured with this technology. The ultra-high-speed 0.5 μm InP DHBT technology offers a combination of ultra-high-speed and high breakdown voltage, which makes it an ideal candidate for next generation 100 GHz+mixed signal integrated circuits.     

A 60 GHz phased array with measurement and de-embedding techniques

We present a 60 GHz phased array system that combines several key technologies to realize 10 GHz bandwidth coverage. Particularly, a tightly coupled dipole array centered at 60 GHz is designed and tested for its wideband performance. The tightly coupled dipole elements offer excellent wideband behavior of 10 GHz with voltage standing wave ratio?<?3 with scanning to 45°, as well as low cost printed circuit board fabrication. Additionally, we demonstrate a measurement setup with de-embedding procedure to measure gain at the antenna feed point. A feeding structure was designed and fabricated for de-embedding gain pattern measurements. Recovered measurements are shown to be in agreement with simulation.