Characterization of the SnO2 based thin film transistors with Ga, In and Hf doping

We investigated the effects of doping tin oxide thin film transistors (TFTs) with Ga, In, and Hf. The quantity of doping impurities added to the SnO2-TFT channel layer was as follows: Ga (6.3-21.4 at.%), In (9.6-55.6 at.%), and Hf (1.2-2.7 at.%). Hafnium and gallium doping of SnO2 thin film decreased the carrier concentration, possibly due to a decrease in field effect mobility, and reduced oxygen vacancy-related defects. Indium-doped SnO2-TFTs exhibited high performance with a high field-effect mobility of > 20 cm2 V(-1) s(-1). The current on/off ratio and the subthreshold swing of In-doped SnO2-TFTs was 1 x 10(9) and 0.5 V/decade, respectively. These results demonstrate that Ga, In, and Hf doping can effectively enhance the performance of SnO2-based TFT devices.     

A nanoparticulate indium tin oxide field-effect transistor with solid electrolyte gating

Reversible tuning of the transport properties of metallic conducting systems is not reported widely in the literature. Here, we report a junction field-effect transistor (FET) based on a transparent conducting oxide (TCO) nanoparticle channel and a solid polymer electrolyte as a gate. The device principle is based on the variation of the drain current induced by the capacitive double layer charging at the electrolyte/nanoparticle interfaces. A device with a metallic conducting channel made of indium tin oxide (ITO) nanoparticles exhibits an on/off ratio of 2 × 10(3) even when the gate potential is limited within the electrochemical capacitive region to avoid redox reactions at the interface. An FET device with metal-like conductance is always favored for the low dimensions of the device and a high on-state current. The field-effect mobility is calculated to be 24.3?cm(2)?V(-1)?s(-1). A subthreshold swing between 230 and 425?mV?dec(-1) is observed.     

Simulation, fabrication and characterization of ZnO based thin film transistors grown by radio frequency magnetron sputtering

We report the performance of the thin film transistors (TFTs) using ZnO as an active channel layer grown by radio frequency (RF) magnetron sputtering technique. The bottom gate type TFT, consists of a conventional thermally grown SiO2 as gate insulator onto p-type Si substrates. The X-ray diffraction patterns reveal that the ZnO films are preferentially orientated in the (002) plane, with the c-axis perpendicular to the substrate. A typical ZnO TFT fabricated by this method exhibits saturation field effect mobility of about 0.6134 cm2/V s, an on to off ratio of 102, an off current of 2.0 x 10(-7) A, and a threshold voltage of 3.1 V at room temperature. Simulation of this TFT is also carried out by using the commercial software modeling tool ATLAS from Silvaco-International. The simulated global characteristics of the device were compared and contrasted with those measured experimentally. The experimental results are in fairly good agreement with those obtained from simulation.     

Preparation and electrical properties of electrospun tin-doped indium oxide nanowires

Well-aligned tin-doped indium (ITO) nanowires have been prepared using the electrospinning process. The Sn doping mechanism and microstructure have been characterized by x-ray diffraction (XRD) and x-ray photoelectron spectroscopy (XPS). Devices for I-V measurement and field-effect transistors (FETs) were assembled using ITO nanowires with top contact configurations. The effect of Sn doping on the electrical conductivity was significant in that it enhanced the conductance by over 10(7) times, up to ～1?S?cm(-1) for ITO nanowires with an Sn content of 17.5 at.%. The nanowire FETs were operated in the depletion mode with an electron mobility of up to 0.45?cm(2)?V(-1)?s(-1) and an on/off ratio of 10(3).     

Crystal structures and transistor properties of phenyl-substituted tetrathiafulvalene derivatives

The crystal structures, thin-film properties, and field-effect transistor (FET) characteristics of tetrathiafulvalene (TTF) derivatives with two phenyl groups are systematically investigated. The highest mobility, 0.11?cm(2)?V(-1)?s(-1), is observed in biphenyl-substituted TTF (1). The correlation between the crystal structures and the FET properties demonstrates that good transistor properties are associated with two-dimensional intermolecular interaction, which is achieved when the molecules are standing nearly perpendicular to the substrate. Since these TTF derivatives are strong electron donors, the use of a metallic charge-transfer salt (TTF)(TCNQ) as the source and drain electrodes has resulted in a considerable reduction of the off current (TCNQ: tetracyanoquinodimethane).     

Gate insulator effects on the electrical performance of ZnO thin film transistor on a polyethersulphone substrate

Low temperature processing for fabrication of transistor backplane is a cost effective solution while fabrication on a flexible substrate offers a new opportunity in display business. Combination of both merits is evaluated in this investigation. In this study, the ZnO thin film transistor on a flexible Polyethersulphone (PES) substrate is fabricated using RF magnetron sputtering. Since the selection and design of compatible gate insulator is another important issue to improve the electrical properties of ZnO TFT, we have evaluated three gate insulator candidates; SiO2, SiNx and SiO2/SiNx. The SiO2 passivation on both sides of PES substrate prior to the deposition of ZnO layer was effective to enhance the mechanical and thermal stability. Among the fabricated devices, ZnO TFT employing SiNx/SiO2 stacked gate exhibited the best performance. The device parameters of interest are extracted and the on/off current ratio, field effect mobility, threshold voltage and subthreshold swing are 10(7), 22 cm2/Vs, 1.7 V and 0.4 V/decade, respectively.     

Multiwall carbon nanotube and poly(3,4-ethylenedioxythiophene): polystyrene sulfonate (PEDOT:PSS) composite films for transistor and inverter devices

Highly conductive multiwalled carbon nanotube (MWNT)/Poly(3,4-ethylenedioxythiophene) polymerized with poly(4-styrenesulfonate) (PEDOT:PSS) films were prepared by spin coating a mixture solution. The solution was prepared by dispersing MWNT in the PEDOT:PSS solution in water using ultrasonication without any oxidation process. The effect of the MWNT loading in the solution on the film properties such as surface roughness, work function, surface energy, optical transparency, and conductivity was studied. The conductivity of MWNT/PEDOT:PSS composite film was increased with higher MWNT loading and the high conductivity of MWNT/PEDOT:PSS films enabled them to be used as a source/drain electrode in organic thin film transistor (OTFT). The pentacene TFT with MWNT/PEDOT:PSS S/D electrode showed much higher performance with mobility about 0.2 cm2/(V s) and on/off ratio about 5 × 10? compared to that with PEDOT:PSS S/D electrode (～0.05 cm2/(V s), 1 × 10?). The complementary inverters exhibited excellent characteristics, including high gain value of about 30.     

High performance horizontal gate-all-around silicon nanowire field-effect transistors

Semiconducting nanowires have been pointed out as one of the most promising building blocks for submicron electrical applications. These nanometer materials open new opportunities in the area of post-planar traditional metal-oxide-semiconductor devices. Herein, we demonstrate a new technique to fabricate horizontally suspended silicon nanowires with gate-all-around field-effect transistors. We present the design, fabrication and electrical measurements of a high performance transistor with high on current density (～150?μA?μm(-1)), high on/off current ratio (10(6)), low threshold voltage (～?-?0.4?V), low subthreshold slope (～100?mV /dec) and high transconductance (g(m)?～?9.5?μS). These high performance characteristics were possible due to the tight electrostatic coupling of the surrounding gate, which significantly reduced the Schottky-barrier effective height, as was confirmed experimentally in this study.     

High performance field-effect transistors fabricated with laterally grown ZnO nanorods in solution

We have exploited a method for the lateral growth of multiple ZnO nanorods between electrodes in solution without the use of a metal catalyst to fabricate high performance field-effect transistors (FETs). This method enables us to directly align overlapped or overlap-free nanowires between electrodes by eliminating the vertical growth components and complex structural networks. The overlap-free ZnO nanorod FETs showed better performance with a mobility of ～ 8.5 cm(2) V( - 1) s( - 1) and an on/off ratio of ～ 4 × 10(5) than the overlapped ZnO nanorod FETs having a mobility of ～ 5.3 cm(2) V( - 1) s( - 1) and an on/off ratio of ～ 3 × 10(4). All the FETs fabricated in this work showed much better performance than the previously reported solution-based ZnO FETs.     

Application of pulsed laser deposited zinc oxide films to thin film transistor device

Transparent zinc oxide (ZnO) thin films were deposited on various substrates using a pulsed laser deposition (PLD) technique. During the PLD, oxygen pressure and substrate temperature were varied in order to find an optimal preparation condition of ZnO for thin film transistor (TFT) application. Dependence of optical, electrical and crystalline properties on the deposition conditions was investigated. The ZnO thin films were then deposited on SiN/c-Si layer structures in order to fabricate a TFT device. The pulsed laser deposited ZnO films showed a remarkable TFT performance: field effect mobility (μ_FE) of 2.4-12.85 cm²/V s and ratio of on and off current (R_on/off) in 2-6 order range. Influence of ZnO preparation conditions on the resulting TFT performance was discussed.     

Solution-processed zinc oxide field-effect transistors based on self-assembly of colloidal nanorods

Colloidal zinc oxide (ZnO) nanocrystals are attractive candidates for a low-temperature and solution-processible semiconductor for high-performance thin-film field-effect transistors (TFTs). Here we show that by controlling the shape of the nanocrystals from spheres to rods the semiconducting properties of spin-coated ZnO films can be much improved as a result of increasing particle size and self-alignment of the nanorods along the substrate. Postdeposition hydrothermal growth in an aqueous zinc ion solution has been found to further enhance grain size and connectivity and improve device performance. TFT devices made from 65-nm-long and 10-nm-wide nanorods deposited by spin coating have been fabricated at moderate temperatures of 230 degrees C with mobilities of 0.61 cm(2)V(-1)s(-1) and on/off ratios of 3 x 10(5) after postdeposition growth, which is comparable to the characteristics of TFTs fabricated by traditional sputtering methods.     

Fully transparent thin-film transistor devices based on SnO2 nanowires

We report on studies of field-effect transistor (FET) and transparent thin-film transistor (TFT) devices based on lightly Ta-doped SnO2 nano-wires. The nanowire-based devices exhibit uniform characteristics with average field-effect mobilities exceeding 100 cm2/V x s. Prototype nano-wire-based TFT (NW-TFT) devices on glass substrates showed excellent optical transparency and transistor performance in terms of transconductance, bias voltage range, and on/off ratio. High on-currents and field-effect mobilities were obtained from the NW-TFT devices even at low nanowire coverage. The SnO2 nanowire-based TFT approach offers a number of desirable properties such as low growth cost, high electron mobility, and optical transparency and low operation voltage, and may lead to large-scale applications of transparent electronics on diverse substrates.     

Improvement in the bias stability of zinc oxide thin-film transistors using Si3N4 insulator with SiO2 interlayer

The performance of ZnO thin film transistors (TFT) subjected to SiO₂ interlayer treatments on Si₃N₄ insulators was investigated. In the case of a SiO₂ interlayer of 10 nm on Si₃N₄ insulator, a drastic improvement in device performance was obtained. ZnO TFT with this interlayer showed reduced trap density between the Si₃N₄ and ZnO channel, bringing remarkable improvement in bias stability characteristics. These devices show good performance and exhibit a high field-effect mobility of 6.41 cm²/Vs, an on/off current ratio of 10⁸, and a subthreshold swing of 1.46 V/decade. Also, the turn-on voltage shifted from − 2 V to − 6 V with negligible changes in the subthreshold swing and field effect mobility after total stress time.     

On the fabrication of crystalline C(60) nanorod transistors from solution

Flexible and high-aspect-ratio C(60) nanorods are synthesized using a liquid-liquid interfacial precipitation process. As-grown nanorods are shown to exhibit a hexagonal close-packed single-crystal structure, with m-dichlorobenzene solvent molecules incorporated into the crystalline structure in a C(60):m-dichlorobenzene ratio of 3:2. An annealing step at 200?°C transforms the nanorods into a solvent-free face-centred-cubic polycrystalline structure. The nanorods are deposited onto field-effect transistor structures using two solvent-based techniques: drop-casting and dip-coating. We find that dip-coating deposition results in a preferred alignment of non-bundled nanorods and a satisfying transistor performance. The latter is quantified by the attainment of an electron mobility of 0.08?cm (2)?V (-1)?s (-1) and an on/off ratio of >?10(4) for a single-crystal nanorod transistor, fabricated with a solution-based and low-temperature process that is compatible with flexible substrates.     

Hybrid Si nanowire/amorphous silicon FETs for large-area image sensor arrays

Silicon nanowire (SiNW) field-effect transistors (FETs) were fabricated from nanowire mats mechanically transferred from a donor growth wafer. Top- and bottom-gate FET structures were fabricated using a doped a-Si:H thin film as the source/drain (s/d) contact. With a graded doping profile for the a-Si:H s/d contacts, the off-current for the hybrid nanowire/thin-film devices was found to decrease by 3 orders of magnitude. Devices with the graded contacts had on/off ratios of ～10(5), field-effect mobility of ～50 cm(2)/(V s), and subthreshold swing of 2.5 V/decade. A 2 in. diagonal 160 × 180 pixel image sensor array was fabricated by integrating the SiNW backplane with an a-Si:H p-i-n photodiode.     

Fabrication of high performance low temperature poly-silicon backplanes on metal foil for flexible active-matrix organic light emission diode displays

We have developed Low Temperature Poly-Silicon (LTPS) backplanes on metal for flexible 2.8-in. Active-Matrix Organic Light Emission Diode (AM-OLED) displays. The PMOS devices exhibit interesting characteristics such as field-effect mobility of 83 cm²/V.s, on/off current ratio of more than 10⁷, a substhreshold slope of 0.47 V/dec, and a leakage current of 0.02 pA/μm at Vds = 0.1 V. Also, thin film transistors (TFT) characteristics were shown to be very homogeneous across the plates. These good performances are attributed to the possibility of developing an LTPS process on metal very close to the process existing on glass, thanks to the use of plasma enhanced chemical vapour deposition (PECVD) SiO₂ as the thick insulator, which provides to maintain high temperature budget. The influence of the metal substrate as a back-gate was studied as a function of the insulator thickness. Based on simulation and measurements, it was evidenced that the metal potential can have a significant influence on the TFT operation. Overall, this self-aligned LTPS process on metal seems to be very promising for the manufacturing of high quality and high resolution flexible AM-OLED displays.     

High-performance ZnO thin-film transistors with location-controlled crystal grains fabricated by low-temperature hydrothermal method

In this paper, high-performance bottom-gate (BG) thin-film transistors (TFTs) with zinc oxide (ZnO) artificially location-controlled lateral grain growth have been prepared via low-temperature hydrothermal method. For the proper design of source/drain structure of ZnO/Ti/Pt thin films, the grains can be laterally grown from the under-cut ZnO beneath the Ti/Pt layer. Consequently, the single one vertical grain boundary perpendicular to the current flow will be produced in the channel region as the grown grains from the source/drain both sides are impinged. As compared with the conventional sputtered ZnO BG-TFTs, the proposed location-controlled hydrothermal ZnO BG-TFTs (W/L = 250 microm/10 microm) demonstrated the higher field-effect mobility of 6.09 cm2/V x s, lower threshold voltage of 3.67 V, higher on/off current ratio above 10(6), and superior current drivability, reflecting the high-quality ZnO thin films with less grain boundary effect in the channel region.     

Corrugated Heterojunction Metal‐Oxide Thin‐Film Transistors with High Electron Mobility via Vertical Interface Manipulation

A new strategy is reported to achieve high‐mobility, low‐off‐current, and operationally stable solution‐processable metal‐oxide thin‐film transistors (TFTs) using a corrugated heterojunction channel structure. The corrugated heterojunction channel, having alternating thin‐indium‐tin‐zinc‐oxide (ITZO)/indium‐gallium‐zinc‐oxide (IGZO) and thick‐ITZO/IGZO film regions, enables the accumulated electron concentration to be tuned in the TFT off‐ and on‐states via charge modulation at the vertical regions of the heterojunction. The ITZO/IGZO TFTs with optimized corrugated structure exhibit a maximum field‐effect mobility >50 cm² V^?1 s^?1 with an on/off current ratio of >10⁸ and good operational stability (threshold voltage shift <1 V for a positive‐gate‐bias stress of 10 ks, without passivation). To exploit the underlying conduction mechanism of the corrugated heterojunction TFTs, a physical model is implemented by using a variety of chemical, structural, and electrical characterization tools and Technology Computer‐Aided Design simulations. The physical model reveals that efficient charge manipulation is possible via the corrugated structure, by inducing an extremely high carrier concentration at the nanoscale vertical channel regions, enabling low off‐currents and high on‐currents depending on the applied gate bias.     

Low operating voltage single ZnO nanowire field-effect transistors enabled by self-assembled organic gate nanodielectrics

The development of nanowire transistors enabled by appropriate dielectrics is of great interest for flexible electronic and display applications. In this study, nanowire field-effect transistors (NW-FETs) composed of individual ZnO nanowires are fabricated using a self-assembled superlattice (SAS) as the gate insulator. The 15-nm SAS film used in this study consists of four interlinked layer-by-layer self-assembled organic monolayers and exhibits excellent insulating properties with a large specific capacitance, 180 nF/cm2, and a low leakage current density, 1 x 10(-8) A/cm2. SAS-based ZnO NW-FETs display excellent drain current saturation at Vds = 0.5 V, a threshold voltage (Vth) of -0.4 V, a channel mobility of approximately 196 cm2/V s, an on-off current ratio of approximately 10(4), and a subthreshold slope of 400 mV/dec. For comparison, ZnO NW-FETs are also fabricated using 70-nm SiO2 as the gate insulator. Implementation of the SAS gate dielectric reduces the NW-FET operating voltage dramatically with more than 1 order of magnitude enhancement of the on-current. These results strongly indicate that SAS-based ZnO NW-FETs are promising candidates for future flexible display and logic technologies.     

Extracting transport parameters in GaAs nanopillars grown by selective-area epitaxy

We investigate the transport properties in p-type GaAs nanopillars (NPs) grown on GaAs(111) B substrates using selective-area epitaxy by studying single-NP field-effect transistors. Experimental results indicate that normalized resistance and field-effect mobility are highly sensitive to NP dimensions. Both in situ and ex?situ chemical surface passivation techniques are found to significantly improve conductivity and mobility, especially for the smaller diameter NPs. A semi-empirical model based on diameter dependent mobility is used to extract actual doping levels and surface state density by fitting normalized resistance as a function of NP diameter. Surface state densities before and after passivation are found to be 5?×?10(12)?cm(-2)?eV(-1) and 7?×?10(10)?cm(-2)?eV(-1), respectively.