共查询到19条相似文献,搜索用时 125 毫秒
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本文使用S3C2440芯片和其内部的RTC芯片实现电子时钟系统的设计。介绍S3C2440内部RTC时钟芯片的工作原理,以及程序实现的过程。 相似文献
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晶体控制振荡器主要用于稳定时钟发生器的时间频率,它可为数据处理设备提供时钟信号。因为基于微处理器的设备通常都有内置的计时功能,因此在无线设备中一般应用有晶体控制振荡器。 或许因为晶体控制振荡器普遍应用于无线设备里,通常很少提及振荡器的基本工作原理。本文概括介绍晶体振荡器的设计和特性方面的基本知识,可能对于工程师们在新产品开发过程中采用晶体振荡器能有所帮助。 相似文献
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与传统的石英时钟元件相比,硅MEMS振荡器具有更小的尺寸、更高的可靠性和更低的功耗,特别适合诸如智能手机、平板电脑以及可穿戴式移动设备等对体积和功耗敏感的应用。几乎所有的电子产品系统都需要时钟,并且系统越复杂需要的时钟器件就越多。一直以来以石英晶体为基础的振荡器、谐振器等是电子系统主要的时钟参考元件,受到电子产品体积越来越小、系统越来越复杂等趋势的影响,时钟元件也必须往小巧、低功耗、高集成度的 相似文献
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Yongping Xia 《电子设计技术》2001,(8)
很多系统采用手表使用的32.768kHz晶振振荡器。但是,用电池驱动的32kHz振荡器可能会消耗掉较大的电源功率。减少功耗等于是延长电池寿命和减小电池体积以及产品体积。Ricoh公司(www.ricoh.com)生产了包括RS5C372B在内的10多种实时时钟芯片(图1)。该器件为内置振荡器的8引脚IC,具有可编程周期中断功能和μC的I~2C接口功能。图1所示电路仅使用了实时时钟芯片的32kHz振荡器功 相似文献
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DDS技术在高频石英晶体测试系统中的应用 总被引:1,自引:1,他引:0
在此介绍了一种以DDS芯片AD9912作为信号源的高频石英晶体测试系统。AD9912是一款直接数字频率合成芯片。一方面,AD9912内部时钟速度可高达1GSPS,并集成了14位数/模转换器,可以直接输出400MHz信号;另一方面,AD9912的频率控制字为48位,可以小于4μHz的分辨率输出信号。由于采用了DDS芯片AD9912作为信号源,所设计的石英晶体测试系统能够在20kHz~400MHz范围内测试石英晶体的串联谐振频率。与国内目前普遍使用的基于振荡器和阻抗计测试方法的测试仪相比,该测试系统具有测试频率范围宽、重复精度高等优点。 相似文献
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Since the fields inside a laser cavity are much higher than the external fields, an analysis of a parametric oscillator with the nonlinear crystal internal to the laser is performed. Using self-consistency equations as the starting point, the equations of motion of such an oscillator are derived. Depending on various cavity, pumping, and nonlinearity parameters, these lead to several types of oscillation with distinctly different operating characteristics: (1) efficient parametric oscillation similar to that of previous analyses; (2) inefficient parametric oscillation resulting from the fact that the nonlinear interaction drives the phases rather than the amplitudes of the signal, idler, and pump; and (3) a pulsing output from the oscillator with repetitive pulses of the signal and idler. A stability analysis of these various regions shows that they are mutually exclusive and can be experimentally chosen by changing the laser gain, the oscillator output coupling, or the strength of the nonlinear interaction. It is shown that the internal oscillator efficiency rapidly approaches the Manley-Rowe limit, as the available pump power becomes several times greater than that required for threshold. The efficiency of an external oscillator having a triply resonant optical cavity is found to be generally less than that of the corresponding internal oscillator. 相似文献
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设计了一种用于时钟芯片的Pierce晶体振荡器,通过对传统结构的改进,增加了振幅控制结构和输出频率校准电路,提高了输出频率、振幅的稳定性和输出频率的精度,降低了功耗。同时对电路的工作原理进行了理论分析,电路采用CSMC 0.5 μm-5 V CMOS工艺实现,通过仿真结果验证,显示该设计达到了技术指标要求。 相似文献
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A digitally temperature-compensated crystal oscillator 总被引:1,自引:0,他引:1
Achenbach R. Feuerstack-Raible M. Hiller F. Keller M. Meier K. Rudolph H. Saur-Brosch R. 《Solid-State Circuits, IEEE Journal of》2000,35(10):1502-1506
The base frequency of oscillators used in the Global System for Mobile Communication (GSM) network or Global Positioning System (GPS) receiver applications needs to be very stable with respect to temperature and supply-voltage variations. One approach to obtain extremely good frequency stability is the use of oven-stabilized crystal oscillators. With this kind of oscillator, a frequency stability versus temperature of a few ppb versus the standard temperature range can be achieved. In this paper, a digitally compensated crystal oscillator is described. The system provides a frequency stability of (Δf)/f<1.5 ppm for a temperature range of -40°C to 90°C compared to about ±20 ppm for a noncompensated crystal. The core of the system is an application-specified integrated circuit (ASIC) fabricated in a standard 0.8-μm CMOS process. The power consumption for the oscillator running at 13 MHz is 100 mW. The final device equipped with the ASIC, crystal blank, and a few external components fits into a 14×9×3 mm3 package 相似文献
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A high-frequency integrated CMOS phase-locked loop (PLL) including two phase detectors is presented. The design integrates a voltage-controlled oscillator, a multiplying phase detector, a phase-frequency detector, and associated circuitry on a single die. The loop filter is external for flexibility and can be a simple passive circuit. A 2-μm CMOS p-well process was used to fabricate the circuit. The loop can lock on input frequencies in excess of 200 MHz with either or both detectors and consumes 500 mW from a single 5-V supply. The oscillator is a ring of three inverting amplifiers and draws from an internal supply voltage regulated by an on-chip bandgap reference. This combination serves to reduce the supply and temperature sensitivity is less than 5%/V, and the oscillator temperature variation is 2.2% in the range of 25 to 80°C. The typical oscillator tuning range is 112 to 209 MHz. The multiplying phase detector and phase-frequency detector exhibit input-referred phase offsets of <4° and -24°, respectively. A numerical system simulation program was written to explore the time-domain behavior of an idealized model based on the PLL design 相似文献
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在计算机的实验中,晶体在温度试验条件下,性能不稳定,导致计算机无法正常工作。通过对晶体的失效分析,确定了晶体失效的原因。结果表明:由于晶体谐振器内部晶片的形成结构异常造成晶体谐振器与振荡电路不能相互匹配,因而在低温条件下表现出来,这种晶体谐振器内部晶片结构异常是导致计算机无法正常工作的原因。通过对晶体谐振器进行温度频差测试,发现晶体谐振器早期失效问题,可解决这一问题,验证试验表明这一措施有效、可行。 相似文献